This answer record lists the known issues for the XST tool in the ISE Design Suite 14.x releases.
Each known issue includes a link to another answer record that contains additional information on the issue.
14.1 XST Resolved Issues
| (Xilinx Answer 46350) | XST - Runs out of stack space even when set to 32M |
| (Xilinx Answer 41013) | 13.1 XST - DSP48E not inferred correctly when using MAC with subtraction |
| (Xilinx Answer 46318) | 13.4 - XST: option IOB = FORCE does not work the same as IOB = TRUE |
| (Xilinx Answer 44586) | 13.2 Verilog $clog2 function implemented improperly |
14.2 XST Resolved Issues
| (Xilinx Answer 47226) | XST does not support asymmetric RAMs for port widths that are non power of 2 |
14.2 XST Known Issues
| (Xilinx Answer 47073) | 13.4 XST - "ERROR:HDLCompiler:1128" is incorrectly given during Synthesis |
| (Xilinx Answer 42228) | 13.1 XST - XST is inserting BUFG on local clock signals when additional ChipScope core logic is added to the design |
| (Xilinx Answer 44372) | 13.3 - "ERROR:HDLCompiler:69 - "<*>.v" Line 24: <TESTONE> is not declared" |
| (Xilinx Answer 46565) | 13.4 XST - Dummy port "p1" added by XST in the absence of the port in the original design |
| (Xilinx Answer 46162) | 13.4 XST -Fails dynamic shift registers for sizes (2^n)+1 for n>=5 |
| (Xilinx Answer 45245) | 13.3 XST - Verific Parser save net attribute prevents SRL inference even if value is "false" |
| (Xilinx Answer 44282) | 13.2 XST - Derived constraints for MMCM are not taken into consideration during optimization |
| (Xilinx Answer 53319) | ISE 14.x XST - Can 14.2 XST handle writing of different data to the same address under different conditions with reference to a memory description? |
14.3 XST Known Issues
| (Xilinx Answer 47073) | 13.4 XST - "ERROR:HDLCompiler:1128" is incorrectly given during Synthesis |
| (Xilinx Answer 42228) | 13.1 XST - XST is inserting BUFG on local clock signals when additional ChipScope core logic is added to the design |
| (Xilinx Answer 44372) | 13.3 - "ERROR:HDLCompiler:69 - "<*>.v" Line 24: <TESTONE> is not declared" |
| (Xilinx Answer 46565) | 13.4 XST - Dummy port "p1" added by XST in the absence of the port in the original design |
| (Xilinx Answer 46162) | 13.4 XST -Fails dynamic shift registers for sizes (2^n)+1 for n>=5 |
| (Xilinx Answer 45245) | 13.3 XST - Verific Parser save net attribute prevents SRL inference even if value is "false" |
| (Xilinx Answer 44282) | 13.2 XST - Derived constraints for MMCM are not taken into consideration during optimization |
| (Xilinx Answer 53319) | ISE 14.x - XST - Can 14.2 XST handle writing of different data to the same address under different conditions with reference to a memory description? |
14.4 XST Resolved Issues
| (Xilinx Answer 53319) | ISE 14.x - XST - Can 14.2 XST handle writing of different data to the same address under different conditions with reference to a memory description? |
14.4 XST Known Issues
| (Xilinx Answer 47073) | 13.4 XST - "ERROR:HDLCompiler:1128" is incorrectly given during Synthesis |
| (Xilinx Answer 42228) | 13.1 XST - XST is inserting BUFG on local clock signals when additional ChipScope core logic is added to the design |
| (Xilinx Answer 44372) | 13.3 - "ERROR:HDLCompiler:69 - "<*>.v" Line 24: <TESTONE> is not declared" |
| (Xilinx Answer 46565) | 13.4 XST - Dummy port "p1" added by XST in the absence of the port in the original design |
| (Xilinx Answer 46162) | 13.4 XST - Fails dynamic shift registers for sizes (2^n)+1 for n>=5 |
| (Xilinx Answer 45245) | 13.3 XST - Verific Parser save net attribute prevents SRL inference even if value is "false" |
| (Xilinx Answer 44282) | 13.2 XST - Derived constraints for MMCM are not taken into consideration during optimization |
14.5 XST Resolved Issues
| (Xilinx Answer 54218) | ISE 14.4 - XST generates incorrect logic resulting in a simulation mismatch on the adder tree |
14.5 XST Known Issues
| (Xilinx Answer 47073) | 13.4 XST - "ERROR:HDLCompiler:1128" is incorrectly given during Synthesis |
| (Xilinx Answer 42228) | 13.1 XST - XST is inserting BUFG on local clock signals when additional ChipScope core logic is added to the design |
| (Xilinx Answer 44372) | 13.3 - "ERROR:HDLCompiler:69 - "<*>.v" Line 24: <TESTONE> is not declared" |
| (Xilinx Answer 46565) | 13.4 XST - Dummy port "p1" added by XST in the absence of the port in the original design |
| (Xilinx Answer 46162) | 13.4 XST -Fails dynamic shift registers for sizes (2^n)+1 for n>=5 |
| (Xilinx Answer 45245) | 13.3 XST - Verific Parser save net attribute prevents SRL inference even if value is "false" |
| (Xilinx Answer 44282) | 13.2 XST - Derived constraints for MMCM are not taken into consideration during optimization |
14.6 XST Resolved Issues
| (Xilinx Answer 54218) | ISE 14.4 - XST generates incorrect logic resulting in a simulation mismatch on the adder tree |
14.6 XST Known Issues
| (Xilinx Answer 47073) | 13.4 XST - "ERROR:HDLCompiler:1128" is incorrectly given during Synthesis |
| (Xilinx Answer 42228) | 13.1 XST - XST is inserting BUFG on local clock signals when additional ChipScope core logic is added to the design |
| (Xilinx Answer 44372) | 13.3 - "ERROR:HDLCompiler:69 - "<*>.v" Line 24: <TESTONE> is not declared" |
| (Xilinx Answer 46565) | 13.4 XST - Dummy port "p1" added by XST in the absence of the port in the original design |
| (Xilinx Answer 46162) | 13.4 XST -Fails dynamic shift registers for sizes (2^n)+1 for n>=5 |
| (Xilinx Answer 45245) | 13.3 XST - Verific Parser save net attribute prevents SRL inference even if value is "false" |
| (Xilinx Answer 44282) | 13.2 XST - Derived constraints for MMCM are not taken into consideration during optimization |
14.7 XST Resolved Issues
| (Xilinx Answer 54218) | ISE 14.4 - XST generates incorrect logic resulting in a simulation mismatch on the adder tree |
14.7 XST Known Issues
| (Xilinx Answer 47073) | 13.4 XST - "ERROR:HDLCompiler:1128" is incorrectly given during Synthesis |
| (Xilinx Answer 42228) | 13.1 XST - XST is inserting BUFG on local clock signals when additional ChipScope core logic is added to the design |
| (Xilinx Answer 44372) | 13.3 - "ERROR:HDLCompiler:69 - "<*>.v" Line 24: <TESTONE> is not declared" |
| (Xilinx Answer 46565) | 13.4 XST - Dummy port "p1" added by XST in the absence of the port in the original design |
| (Xilinx Answer 46162) | 13.4 XST -Fails dynamic shift registers for sizes (2^n)+1 for n>=5 |
| (Xilinx Answer 45245) | 13.3 XST - Verific Parser save net attribute prevents SRL inference even if value is "false" |
| (Xilinx Answer 44282) | 13.2 XST - Derived constraints for MMCM are not taken into consideration during optimization |