In 7 Series, UltraScale, and UltraScale+ devices, what state are the I/Os in after all of the power rails are powered and before configuration?
The 7 Series, UltraScale and UltraScale+ FPGA data sheets state the following:
The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on.
The 7 Series, UltraScale, and UltraScale+ FPGAs contain a pin called PUDC_B. When PUDC_B is Low, internal pull-up resistors are enabled on each SelectIO pin.
When PUDC_B is High, internal pull-up resistors are disabled on each SelectIO pin. The state of this pin effects the state of the I/O from power-on until configuration completes. Therefore, the I/Os will be 3-stated after power-on when PUDC is High.
The state of the I/O prior to the rails being powered is not guaranteed.
Note: due to the presence of the clamp diode, if the I/Os are driven before Vcco is powered this will reverse bias the Vcco rail.
For further information, see (Xilinx Answer 45985).
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 45985 | 7 Series - How do you limit reverse biasing of VCCO when input is being driven by a 3.3V signal before Vcco is powered? | N/A | N/A |
| 51834 | SelectIO Design Assistant - Reliability and over driving IOs. | N/A | N/A |