2. 技术支持
  3. AR# 5108: FPGA Configuration - What is the status of used I/O for Spartan/Virtex families during configuration?
  4. AR# 51088: Vivado Synthesis - For True Dual Port RAM coding styles, does the Vivado Synthesis tool generate RAMs when both ports are specified in the same always/process block?

AR# 51088

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Vivado Synthesis - For True Dual Port RAM coding styles, does the Vivado Synthesis tool generate RAMs when both ports are specified in the same always/process block?

描述

For a True Dual Port RAM, Vivado Synthesis tool does not result in creation of RAMs when both ports are specified in the same always/process block.

解决方案

Currently, there is no specified date to resolve this issue.

As part of the work-around, Xilinx recommends that you put writes and reads for the two different ports in separate always/process blocks.

This answer record will be updated when a permanent resolution is available.

AR# 51088
日期 06/03/2013
状态 Active
Type 综合文章
Tools
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