AR# 54436

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LogiCORE IP AXI UART16550 - Release Notes and Known Issues for Vivado 2013.4 and older tool versions

描述

This answer record contains the Release Notes and Known Issues for the AXI UART16550 and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.4 and older tool versions
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

LogiCORE AXI UART16550 IP Page:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/axi_uart16550.html

解决方案

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
2.0 2013.1
1.01.a 2012.4


General Guidance

The table below provides answer records for general guidance when using the LogiCORE AXI UART16550.

Answer Record Title
(Xilinx Answer 55248) Vivado Timing and IP Constraints


Known and Resolved Issues

The following table provides known issues for the AXI UART16550, starting with v2.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

There are no known issues for Vivado 2013.4.

Answer Record Title Version Found Version Resolved

Revision History
04/03/2013 - Initial release
12/18/2013 - Updated for 2013.4

AR# 54436
日期 03/19/2015
状态 Active
Type 版本说明
Tools
IP
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