When using v11.0 XAUI core configured for 20G DXAUI, marginal timing has been seen when targeting Artix-7 devices.
解决方案
When small timing failures are seen, changing Vivado Synthesis and Implementation tool options have been seen to result in passing timing. Some possibilities include:
In Implementation Settings under Place Design, set the directive to ExtraPostPlacementOpt.
In Synthesis Settings, change control_set_opt_threshold to 60.