This answer record contains the Release Notes and Known Issues for the XAUI Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
The last supported Vivado release of the XAUI core is version 12.3 (Rev. 6) in Vivado 2019.1.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
LogiCORE XAUI Core IP Page:
General Information
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v12.6 (Rev. 6) | 2019.1 |
| v12.3 (Rev. 5) | 2018.3 |
| v12.3 (Rev. 4) | 2018.2 |
| v12.3 (Rev. 3) | 2018.1 |
| v12.3 (Rev. 2) | 2017.4 |
| v12.3 (Rev. 1) | 2017.3 |
| v12.3 | 2017.2 |
| v12.2 (Rev. 8) | 2017.1 |
| v12.2 (Rev. 7) | 2016.4 |
| v12.2 (Rev. 6) | 2016.3 |
| v12.2 (Rev. 5) | 2016.2 |
| v12.2 (Rev. 4) | 2016.1 |
| v12.2 (Rev. 3) | 2015.4 |
| v12.2 (Rev. 2) | 2015.3 |
| v12.2 (Rev. 1) | 2015.2 |
| v12.2 | 2015.1 |
| v12.1 (Rev. 4) | 2014.4 |
| v12.1 (Rev. 3) | 2014.3 |
| v12.1 (Rev. 2) | 2014.2 |
| v12.1 (Rev. 1) | 2014.1 |
| v12.1 | 2013.4 |
| v12.0 | 2013.3 |
| v11.0 (Rev. 1) | 2013.2 |
| v11.0 | 2013.1 |
| v10.4 | 2012.2 |
| v10.3 | 2012.1 |
General Guidance
The table below provides Answer Records for general guidance when using the LogiCORE XAUI core.
| Answer Record | Title |
|---|---|
| (Xilinx Answer 38279) | Ethernet IP Solution Center |
| (Xilinx Answer 33596) | XAUI Frequently Asked Questions (FAQ) |
| (Xilinx Answer 55077) | Ethernet IP Cores - Design Hierarchy in Vivado |
Known and Resolved Issues
The following table provides known issues for the XAUI core, starting with v11.0, initially released in the Vivado 2013.1 tool.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 71454) | This core is being deprecated and will no longer be available starting in Vivado 2019.2 | v12.6 (Rev. 6) | NA |
| (Xilinx Answer 66941) | DXAUI Core Example Design fails in Simulation | v12.2(Rev.2) | v12.2(Rev.3) |
| UltraScale - GTRXRESET required after entering or exiting GT Near-end PMA loopback | v12.0 | v12.2 | |
| (Xilinx Answer 62354) | GTRXRESET toggles when using transceiver debug PRBS inputs | v12.0 | v12.2 |
| (Xilinx Answer 62351) | GTP and GTH - Simulation not supported with Unifast model or SIM_GTRESET_SPEEDUP | v10.4 | NA |
| (Xilinx Answer 59912) | Additional XDC constraints for the MDIO signal inputs to ease timing closure | v12.1 | v12.1 (Rev. 1) |
| (Xilinx Answer 59292) | TX Phase Alignment statemachine not reset on falling edge of powerdown | v12.0 | v12.1 (Rev. 1) |
| (Xilinx Answer 59861) | GTP and GTH - Production reset DRP sequence could get in hung state that requires reconfiguration to recover | v12.0 | v12.1 (Rev. 1) |
| (Xilinx Answer 59860) | 7 Series GTP/GTH - Update to hold off further resets to GTs during reset_in_progress | v12.0 | v12.1 (Rev. 1) |
| (Xilinx Answer 58083) | Update to 7 Series GTX Transceiver attribute - RXDFEXYDEN | v10.4 | v12.0 |
| (Xilinx Answer 56312) | Update to 7 Series GTP/GTH reset logic | v11.0 (Rev. 1) | v12.0 |
| (Xilinx Answer 55132) | Artix-7 - 20G DXAUI - Marginal timing seen | v11.0 | Work-around in Answer Record |
| (Xilinx Answer 55837) | Update to RX termination for 7 Series GTP and GTH | v11.0 | v11.0 (Rev. 1) |
| (Xilinx Answer 55226) | Critical Warning - No cells match DRP path for false path constraint | v11.0 | v11.0 (Rev. 1) |
| (Xilinx Answer 55009) | 7 Series GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode | v10.4 | v11.0 |
| (Xilinx Answer 53779) | Virtex-7 GTH Transceiver - RX Reset Sequence Requirement for Production Silicon | v10.4 | v11.0 |
| (Xilinx Answer 53561) | Artix-7 - RX Reset Sequence Requirement for Production Silicon | v10.4 | v11.0 |
| (Xilinx Answer 50848) | 7 Series GT Transceivers - Reset maybe needed after disabling Loopback | v10.3 | v11.0 |
| (Xilinx Answer 50795) | 7 Series - Timing failures might occur in XAUI Example Design | v10.4 | v11.0 |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 55009 | 面向 7 系列 FPGA GTX/GTH/GTP 收发器的设计咨询：缓冲旁路模式下的 TX 同步控制器相位调整更改 | N/A | N/A |
| AR# 54666 | |
|---|---|
| 日期 | 12/09/2020 |
| 状态 | Active |
| Type | 版本说明 |
| Tools | |
| IP | |