AR# 55135

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Vivado Synthesis - Unsupported SystemVerilog Constructs

描述

This answer record lists the SystemVerilog constructs and features that are not supported by Vivado Synthesis.

解决方案

Vivado Synthesis does not support the following SystemVerilog supported constructs and features:

  • Alias
  • Arrays of Interfaces
  • Dynamic Arrays
  • Assert Statements
  • Class
  • Virtual Ports
  • Virtual Functions
  • Unpacked Unions
  • Tagged Unions in Loops
  • Hierarchical reference to any interface with a given modport name - For example: interface_name.modport_name reference_name

 

AR# 55135
日期 10/08/2014
状态 Active
Type 已知问题
Tools
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