面向 Vivado 综合的 Xilinx 解决方案中心

设计助手

Xilinx Solution Center for Vivado Synthesis - Design Assistant

The Design Assistant walks you through the recommended design flow for Vivado Synthesis while debugging commonly encountered issues. The Design Assistant not only provides useful design and troubleshoot information, but also points you to the exact documentation you need to read to help you design efficiently with Vivado Synthesis.

Note: This answer record is part of Xilinx Vivado Synthesis Solution Center (Xilinx Answer 55265). The Xilinx Vivado Synthesis Solution Center is available to address all questions related to Vivado Synthesis. Whether you are starting a new design with Vivado Synthesis or troubleshooting a problem, use the Solution Center to guide you to the right information.

The Design Assistant for Vivado Synthesis has the following major categories:

For help with Vivado Synthesis SystemVerilog support, see (Xilinx Answer 51360).

This section describes Vivado Synthesis supported systemverilog constructs and provides coding examples for them, which can be used as a reference by the user in their designs.

For help with Vivado Synthesis supported HDL Synthesis attributes, see (Xilinx Answer 55160).

This section describes Vivado Synthesis supported HDL synthesis attributes and provides coding examples for them, which can be used as a reference by the user.in their designs.

For help with Vivado Synthesis switch options used by synth_design TCL, see (Xilinx Answer 55182).

This section describes synth_design TCL command and its associated switch options supported by Vivado Synthesis.

For help with Vivado Synthesis equivalent RTL/GUI/TCL options for XST, see (Xilinx Answer 55185).

This section provides information on Vivado Synthesis's switch options (RTL, GUI, TCL) equivalent to XST. The section provides a tabular column comparing XST and Vivado Synthesis switch options which can be used as a reference by the user when transitioning from XST to Vivado Synthesis.

For help with Vivado Synthesis XDC synthesis attributes & timing constraints Support, see (Xilinx Answer 55260).

This section describes Vivado Synthesis supported XDC synthesis attributes, timing constraints and provides coding examples for them, which can be used as a reference by the user in their designs.

技术文档

面向 Vivado 综合的 Xilinx 解决方案中心 - 文档

使用 Vivado 综合时，敬请参考以下文档。

注: 本答复记录是 Xilinx Vivado 综合解决方案中心的一部分 (Xilinx 答复 55265) 并可用于解决与 Vivado 综合相关的所有问题。无论您是要使用 Vivado 综合来进行新设计还是要调试问题，请使用 Vivado 综合解决方案中心来指导您获取相应的信息。

用户指南

2013.2 Vivado 综合用户指南 (UG901):
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_2/ug901-vivado-synthesis.pdf

2013.1 Vivado 综合用户指南 (UG901):
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_1/ug901-vivado-synthesis.pdf

常见问题

Xilinx Solution Center for Vivado Synthesis - Top Issues