2. 技术支持
  3. AR# 5535: 1.5i Virtex Timing - Speed numbers for horizontal long lines are being underestimated.
  4. AR# 55357: 7 Series Integrated Block for PCI Express v1.8 - How do you allow messages and legacy interrupts to be routed to the root port?

AR# 55357

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7 Series Integrated Block for PCI Express v1.8 - How do you allow messages and legacy interrupts to be routed to the root port?

描述

If generating legacy interrupt messages, the root complex receives interrupt messages but the corresponding control signals (tvalid, tkeep, tuser, etc.) do not assert.

解决方案

To enable message routing, the ENABLE_MSG_ROUTE attribute needs to be set to the following value:

parameter [10:0] ENABLE_MSG_ROUTE = 11'b00000001000,

PCI Express Endpoint Implementation

For this implementation, in simulation, DSPORT (Xilinx Root Complex simulation model) will be the root complex.
Users will need to find and edit the ENABLE_MSG_ROUTE attribute as shown above in the /<project_directory>/<core_directory>/simulation/dsport/pcie_2_1_rport_7x.v(hd) file.

PCI Express Root Port Implementation

Users will need to find and edit the ENABLE_MSG_ROUTE attribute as shown above in their Root Port PCIe core top level located at: /<project_directory>/<core_directory>/source/<core_name>.v(hd) file.

Revision History
5/7/2013 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54643 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 55357
日期 08/26/2013
状态 Active
Type 已知问题
IP
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