AR# 56174

Kintex-7 FPGA Embedded Targeted Reference Design - Release Notes and Known Issues Master Answer Record

描述

This answer record contains the Release Notes and Known Issues for the Targeted Reference Design shipped with the Kintex-7 FPGA Embedded Kit. The nature of this content is to help you avoid running into issues when performing intended operations within the TRD.

For Release Notes and Known Issues for the Kintex-7 FPGA Embedded Kit, please see (Xilinx Answer 52970).

The Kintex-7 FPGA Embedded Kit v1.0 includes the following components.

软件

ISE Design Suite

硬件

KC705 board with a Kintex-7 FPGA XC7K325T-2FFG900CES device
The Kintex-7 FPGA Connectivity Kit TRD v1.2 and beyond targets Kintex-7 FPGA XC7K325T-2FFG900C device

解决方案

Kintex-7 FPGA Embedded Kit TRD v1.0 for ISE Design Suite 13.4 with CES silicon

In order to set the environment variables, namely XILINX and XILINX_PLANAHEAD, it is required that settings32.sh or settings64.sh be sourced from the ISE installation folder. Or, invoke the ISE Design Suite Command Prompt on Windows through the following path in the Start menu --> Xilinx ISE Design Suite 13.4 --> Accessories.

芯片

The kit ships with KC705 board with GES silicon. Refer to the XC7K325T ES Errata for any further information.

IP 核

LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
LogiCORE IP AXI Interconnect (axi_interconnect) : v1.05.a
LogiCORE IP AXI to AXI Connector (axi2axi_connector) : v1.00.a
LogiCORE IP AXI Interrupt Controller (axi_intc) : v1.01.a
LogiCORE IP AXI Timer (axi_timer) : v1.03.a
LogiCORE IP AXI Block RAM Controller (axim_bram_ctrl) : v1.03.a
LogiCORE IP AXI 16550 (axi_uart16550) : v1.01.a
LogiCORE IP AXI GPIO (axi_gpio) : v1.01.b
LogiCORE IP AXI External Memory Controller (axi_emc) : v1.02.a
LogiCORE IP AXI IIC Bus Interface (axi_iic) : v1.01.b
LogiCORE IP AXI DMA (axi_dma) : v5.00.a
LogiCORE IP AXI Ethernet (axi_ethernet) : v3.00.a
LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.00.a. Local pcore.
LogiCORE IP AXI XADC (axi_xadc) : v1.00.a
LogiCORE IP Video Timing Controller (axi_vtc) : v3.00.a. Local pcore.
LogiCORE IP Processor LMB BRAM Interface Controller (lmb_bram_if_cntlr): v3.00.b
Performance Monitor (perf_monitor) : v1.00.a. Local pcore.
IP Processor Local Memory Bus (lmb_v10) : v2.00.b
Block RAM (bram_block) : v1.00.a
MicroBlaze : v8.20.b
MicroBlaze Debug Module (mdm) : v2.00.b
clock_generator : v4.03.a
AXI 7 Series Memory Controller (axi_7series_ddrx) : v1.03.a
Secure Digital (SD) card Host Controller IP core from Xylon logicBRICKS IP core library (logisdhc) : v1.06.c. Third party. Local pcore.
Utility Reduced Logic (util_reduced_logic) : v1.00.a
Utility Flip-Flop (util_flipflop) : v1.10.a
Video Multiplexer (vsrc_sel) : v1.00.a. Local pcore.
AXI Internal Test Pattern Generator (axi_tpg) : v2.00.a. Local pcore.
DVI2AXI (dvi2axi) : v1.00.a. Local pcore.
DVI Scaler : v1.00.a. Local pcore.
Video Scaler (axi_scaler) : v1.00.a. Local pcore.
Compact Video Controller (logicvc) : v2.04.a. Third party. Local pcore.
24bit RGB to 16bit YCbCr converter IP (dvi_24_to_16bit_ycbcr) : v1.00.a. Local pcore.

目标参考设计

Rebuilding the Webserver application could result in errors. For more information, see (Xilinx Answer 54143).
Care needed on path name length. For more information, see (Xilinx Answer 55481).

工具

TRD uses ISE Design Suite 13.4 (Logic or System or Embedded Edition).

Kintex-7 FPGA Embedded Kit TRD v2.0 for ISE Design Suite 14.1 with CES Silicon

In order to set the environment variables, namely XILINX and XILINX_PLANAHEAD, it is required that settings32.sh or settings64.sh be sourced from the ISE installation folder. Or, invoke the ISE Design Suite Command Prompt on Windows through the following path in the Start menu --> Xilinx ISE Design Suite 14.1 --> Accessories.

Silicon

The kit ships with KC705 board with GES silicon. Refer to the XC7K325T ES Errata for any further information.

IP 核

LogiCORE IP Processor System Reset Mdoule (proc_sys_reset) : v3.00.a
LogiCORE IP AXI Interconnect (axi_interconnect) : v1.06.a
LogiCORE IP AXI to AXI Connector (axi2axi_connector) : v1.00.a
LogiCORE IP AXI Interrupt Controller (axi_intc) : v1.02.a
LogiCORE IP AXI Timer (axi_timer) : v1.03.a
LogiCORE IP AXI Block RAM Controller (axim_bram_ctrl) : v1.03.a
LogiCORE IP AXI 16550 (axi_uart16550) : v1.01.a
LogiCORE IP AXI GPIO (axi_gpio) : v1.01.b
LogiCORE IP AXI External Memory Controller (axi_emc) : v1.03.a
LogiCORE IP AXI IIC Bus Interface (axi_iic) : v1.02.a
LogiCORE IP AXI DMA (axi_dma) : v5.00.a
LogiCORE IP AXI Ethernet (axi_ethernet) : v3.01.a. Local pcore.
LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.01.a. Local pcore.
LogiCORE IP AXI XADC (axi_xadc) : v1.00.a
LogiCORE IP Video Timing Controller (axi_vtc) : v3.00.a. Local pcore.
LogiCORE IP Processor LMB BRAM Interface Controller (lmb_bram_if_cntlr): v3.00.b
Performance Monitor (perf_monitor) : v1.00.a. Local pcore.
IP Processor Local Memory Bus (lmb_v10) : v2.00.b
Block RAM (bram_block) : v1.00.a
MicroBlaze : v8.30.b
MicroBlaze Debug Module (mdm) : v2.00.b
clock_generator : v4.03.a
AXI 7 Series Memory Controller (axi_7series_ddrx) : v1.04.a
Secure Digital (SD) card Host Controller IP core from Xylon logicBRICKS IP core library (logisdhc) : v1.06.c. Third party. Local pcore.
Utility Reduced Logic (util_reduced_logic) : v1.00.a
Utility Flip-Flop (util_flipflop) : v1.10.a
Video Multiplexer (vsrc_sel) : v1.00.a. Local pcore.
AXI Internal Test Pattern Generator (axi_tpg) : v2.00.a. Local pcore
DVI2AXI (dvi2axi) : v1.00.a. Local pcore.
DVI Scaler : v1.00.a. Local pcore.
Video Scaler (axi_scaler) : v1.00.a. Local pcore.
Compact Video Controller (logicvc) : v2.04.a. Third party. Local pcore.
24bit RGB to 16bit YCbCr converter IP (dvi_24_to_16bit_ycbcr) : v1.00.a. Local pcore.

目标参考设计

Rebuilding the Webserver application could result in errors. For more information, see (Xilinx Answer 54143).
Care needed on path name length. For more information, see (Xilinx Answer 55481).

工具

TRD uses ISE Design Suite 14.1 (Logic or System or Embedded Edition)

Kintex-7 FPGA Embedded Kit TRD v3.0 for ISE Design Suite 14.2 with C Silicon

芯片

The kit ships with KC705 board with Production silicon.

IP 核

LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
LogiCORE IP AXI Interconnect (axi_interconnect) : v1.06.a
LogiCORE IP AXI to AXI Connector (axi2axi_connector) : v1.00.a
LogiCORE IP AXI Interrupt Controller (axi_intc) : v1.02.a
LogiCORE IP AXI Timer (axi_timer) : v1.03.a
LogiCORE IP AXI Block RAM Controller (axim_bram_ctrl) : v1.03.a
LogiCORE IP AXI 16550 (axi_uart16550) : v1.01.a
LogiCORE IP AXI GPIO (axi_gpio) : v1.01.b
LogiCORE IP AXI External Memory Controller (axi_emc) : v1.03.a
LogiCORE IP AXI IIC Bus Interface (axi_iic) : v1.02.a
LogiCORE IP AXI DMA (axi_dma) : v6.01.a
LogiCORE IP AXI Ethernet (axi_ethernet) : v3.01.a
LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.02.a
LogiCORE IP AXI XADC (axi_xadc) : v1.00.a
LogiCORE IP Processor LMB BRAM Interface Controller (lmb_bram_if_cntlr) : v3.10.a
Performance Monitor (perf_monitor) : v1.00.a. Local pcore.
IP Processor Local Memory Bus (lmb_v10) : v2.00.b
Block RAM (bram_block) : v1.00.a
MicroBlaze : v8.40.a
MicroBlaze Debug Module (mdm) : v2.10.a
clock_generator : v4.03.a
AXI 7 Series Memory Controller (axi_7series_ddrx) : v1.05.a
Secure Digital (SD) card Host Controller IP core from Xylon logicBRICKS IP core library (logisdhc) : v1.06.c. Third party. Local pcore.
Utility Reduced Logic (util_reduced_logic) : v1.00.a
Utility Filp-Flop (util_flipflop) : v1.10.a
Video Multiplexer (vsrc_sel) : v1.00.a. Local pcore.
AXI Internal Test Pattern Generator (axi_tpg) : v2.00.a. Local pcore.
DVI2AXI (dvi2axi) : v1.00.a. Local pcore.
DVI Scaler : v1.00.a. Local pcore.
Video Scaler (axi_scaler) : v1.00.a. Local pcore.
Compact Video Controller (logicvc) : v2.05.a. Third party. Local pcore.
EDK build IP Video Timing Controller (v_tc) : v5.00.a.
Coregen based axi_vtc pcore is replaced with v_tc EDK pcore
v_tc driver compilation may give errors - need to set this as generic / none in the BSP settings
DATA2MEM in SDK with tool generated BMM file may cause errors. For more information, see (Xilinx Answer 51180).

目标参考设计

Rebuilding the Webserver application could result in errors. For more information, see (Xilinx Answer 54143).
Care needed on path name length. For more information, see (Xilinx Answer 55481).

工具

TRD uses ISE Design Suite 14.2 (Logic or System or Embedded Edition)
Tactical Patch required for 7-Series GES -2 devices in 14.2. For more information, see (Xilinx Answer 50886).

Kintex-7 FPGA Embedded Kit TRD v4.0 for ISE Design Suite 14.3 with C Silicon

Vivado flow introduced from this release onwards.

Silicon

The kit ships with KC705 board with Production silicon.

IP 核

LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
LogiCORE IP AXI Interconnect (axi_interconnect) : v1.06.a
LogiCORE IP AXI to AXI Connector (axi2axi connector) : v1.00.a
LogiCORE IP AXI Interrupt Controller (axi_intc) : v1.03.a
LogiCORE IP AXI Timer (axi_timer) : v1.03.a
LogiCORE IP AXI Block RAM Controller (axim_bram_ctrl) : v1.03.a
LogiCORE IP AXI 16550 (axi_uart16550) : v1.01.a
LogiCORE IP AXI GPIO (axi_gpio) : v1.01.b
LogiCORE IP AXI External Memory Controller (axi_emc) : v1.03.a
LogiCORE IP AXI IIC Bus Interface (axi_iic) : v1.02.a
LogiCORE IP AXI DMA (axi_dma) : v6.02.a
LogiCORE IP AXI Ethernet (axi_ethernet) : v3.01.a
LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.03.a
LogiCORE IP AXI XADC (axi_xadc) : v1.00.a
LogiCORE IP Processor LMB BRAM Interface Controller (lmb_bram_if_cntlr) : v3.10.b
Performance Monitor (perf_monitor) : v1.00.a. Local pcore.
IP Processor Local Memory Bus (lmb_v10) : v2.00.b
Block RAM (bram_block) : v1.00.a
MicroBlaze : v8.40.b
MicroBlaze Debug Module (mdm) : v2.10.a
clock_generator : v4.03.a
AXI 7 Series Memory Controller (axi_7series_ddrx) : v1.06.a
Secure Digital (SD) card Host Controller IP core from Xylon logicBRICKS IP core library (logisdhc) : v1.06.c. Third party. Local pcore.
Utility Reduced Logic (util_reduced_logic) : v1.00.a
Utility Flip-Flop (util_flipflop) : v1.10.a
Video Multiplexer (vsrc_sel) : v1.00.a. Local pcore.
AXI Internal Test Pattern Generator (axi_tpg) : v2.00.a. Local pcore.
DVI2AXI (dvi2axi) : v1.00.a. Local pcore.
DVI Scaler : v1.00.a. Local pcore.
Video Scaler (axi_scaler) : v1.00.a. Local pcore.
Compact Video Controller (logicvc) : v2.05.a. Third party. Local pcore.
EDK build IP Video Timing Controller (v_tc) : v5.01.a
v_tc driver compilation may give errors - need to set this as generic / none in the BSP settings
DATA2MEM in SDK with tool generated BMM file may cause errors. For more information, see (Xilinx Answer 51180).

目标参考设计

Rebuilding the Webserver application could result in errors. For more information, see (Xilinx Answer 54143).
Care needed on path name length. For more information, see (Xilinx Answer 55481).
Synthesis fails in Kintex-7 Embedded TRD Vivado flow. For more information, see (Xilinx Answer 53328).

工具

TRD uses ISE Design Suite 14.3 (Logic or System or Embedded Edition)
Tactical Patch required for 7-Series GES -2 devices in 14.3. For more information, see (Xilinx Answer 50886).

Kintex-7 FPGA Embedded Kit TRD v5.0 for ISE Design Suite 14.4 with C Silicon

Vivado flow introduced from this release onwards.

芯片

The kit ships with KC705 board with Production silicon.

IP 核

LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
LogiCORE IP AXI Interconnect (axi_interconnect) : v1.06.a
LogiCORE IP AXI to AXI Connector (axi2axi_connector) : v1.00.a
LogiCORE IP AXI Interrupt Controller (axi_intc) : v1.03.a
LogiCORE IP AXI Timer (axi_timer) : v1.03.a
LogiCORE IP AXI Block RAM Controller (axim_bram_ctrl) : v1.03.a
LogiCORE IP AXI 16550 (axi_uart16550) : v1.01.a
LogiCORE IP AXI GPIO (axi_gpio) : v1.01.b
LogiCORE IP AXI External Memory Controller (axi_emc) : v1.03.a
LogiCORE IP AXI IIC Bus Interface (axi_iic) : v1.02.a
LogiCORE IP AXI DMA (axi_dma) : v6.03.a
LogiCORE IP AXI Ethernet (axi_ethernet) : v3.01.a
LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.04.a
LogiCORE IP AXI XADC (axi_xadc) : v1.00.a
LogiCORE IP Process LMB BRAM Interface Controller (lmb_bram_if_cntlr) : v3.10.b
Performance Monitor _perf_monitor) : v1.00.a. Local pcore.
IP Processor Local Memory Bus (lmb_v1.0) : v2.00.b
Block RAM (bram_block): v1.00.a
MicroBlaze : v8.40.b
MicroBlaze Debug Module (mdm) : v2.10.a
clock_generator : v4.03.a
AXI 7 Series Memory Controller (axi_7series_ddrx): v1.07.a
Secure Digital (SD) card Host Controller IP core from Xylon logBRICKS IP core library (logisdhc) : v1.06c. Third party. Local pcore.
Utility Reduced Logic (util_reduced_logic) : v1.00.a
Utility Flip-Flop (util_flipflop) : v1.10.a
Video Multiplexer (vsrc_sel) : v1.00.a. Local pcore.
AXI Internal Test Pattern Generator (axi_tpg) : v2.00.a. Local pcore.
DVI2AXI (dvi2axi) : v1.00.a. Local pcore.
DVI Scaler : v1.00.a. Local pcore.
Video Scaler (axi_scaler) : v1.00.a. Local pcore
Compact Video Controller (logicvc) : v3.00.a. Third party. Local pcore.
EDK build IP Video Timing Controller (v_tc) : v5.01.a
v_tc driver compilation may give errors - need to set this as generic / none in the BSP settings
DATA2MEM in SDK with tool generated BMM file may cause errors. For more information, see (Xilinx Answer 51180).

目标参考设计

Rebuilding the Webserver application could result in errors. For more information, see (Xilinx Answer 54143).
Care needed on path name length. For more information, see (Xilinx Answer 55481).

工具

TRD uses ISE Design Suite 14.4 (Logic or System or Embedded Edition)
Profiling option is not working in SDK with 14.4 design tools; see (Xilinx Answer 53672).

Kintex-7 FPGA Embedded Kit TRD v6.0 for ISE Design Suite 14.5 with C Silicon

Note: Xilkernel is used as part of this TRD for consistency with previous versions. Xilkernel is in the process of being deprecated and should not be used for new designs.

芯片

The kit ships with KC705 board with Production silicon.

IP 核

LogiCORE IP Processor System Reset Module (proc_sys_reset) : v3.00.a
LogiCORE IP AXI Interconnect (axi_interconnect) : v1.06.a
LogiCORE IP AXI to AXI Connector (axi2axi_connector) : v1.00.a
LogiCORE IP AXI Interrupt Controller (axi_intc) : v1.03.a
LogiCORE IP AXI Timer (axi_timer) : v1.03.a
LogiCORE IP AXI Block RAM Controller (axim_bram_ctrl) : v1.03.a
LogiCORE IP AXI 16550 (axi_uart16550) : v1.01.a
LogiCORE IP AXI GPIO (axi_gpio) : v1.01.b
LogiCORE IP AXI External Memory Controller (axi_emc) : v1.03.b
LogiCORE IP AXI IIC Bus Interface (axi_iic) : v1.02.a
LogiCORE IP AXI DMA (axi_dma) : v6.03.a
LogiCORE IP AXI Ethernet (axi_ethernet) : v3.01.a
LogiCORE IP AXI Video Direct Memory Access (axi_vdma) : v5.04.a
LogiCORE IP AXI XADC (axi_xadc) : v1.00.a
LogiCORE IP AXI Performance Monitor (axi_perf_mon) : v3.00.a
LogiCORE IP Video In to AXI4-Stream (v_vid_in_axi4s) : v2.01.a
LogiCORE IP Processor LMB BRAM Interface Controller (lmb_bram_if_cntlr) : v3.10.c
IP Processor Local Memory Bus (lmb_v10) : v2.00.b
Block RAM (bram_block) : v1.00.a
MicroBlaze : v8.50.a
MicroBlaze Debug Module (mdm) : v2.10.a
clock_generator : v4.03.a
AXI 7 Series Memory Controller (axi_7series_ddrx) : v1.08.a
Secure Digital (SD) card Host Controller IP core from Xylon logicBRICKS IP core library logisdhc) : v1.06.c. Third party. Local pcore.
Utility Reduced Logic (util_reduced_logic) : v1.00.a
Utility Flip-Flop (util_flipflop) : v1.10.a
Video Multiplexer (vsrc_sel) : v1.00.a. Local pcore.
AXI Internal Test Pattern Generator (axi_tpg) : v2.00.a. Local pcore.
DVI Scaler : v1.00.a. Local pcore.
Video Scaler (axi_scaler) : v1.00.a. Local pcore.
Compact Video Controller (logicvc) : v3.00.a. Third party. Local pcore.
EDK build IP Video Timing Controller (v_tc) : v5.01.a
v_tc driver compilation may give errors - need to set this as generic / none in the BSP settings
From this release onwards, local pcore perf_monitor replaced with EDK build IP axi_perf_mon
From this release onwards, local pcore DVI2AXI replaced with v_vid_in_axi4s

目标参考设计

Rebuilding the Webserver application could result in errors. For more information, see (Xilinx Answer 54143).
Care needed on path name length. For more information, see (Xilinx Answer 55481).

Tools

TRD uses ISE Design Suite 14.5 (Logic or System or Embedded Edition)

本答复记录是否对您有帮助？

链接问答记录

主要问答记录

Answer Number	问答标题	问题版本	已解决问题的版本
52970	Kintex-7 FPGA Embedded Kit - Known Issues and Release Notes Master Answer Record	N/A	N/A

AR# 56174
日期	07/01/2013
状态	Active
Type	综合文章
Boards & Kits	Kintex-7 FPGA Embedded Kit

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AR# 56174

Kintex-7 FPGA Embedded Targeted Reference Design - Release Notes and Known Issues Master Answer Record

描述

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