AR# 56625

描述

In Vivado Design Suite 2013.2, if using the Tri-Mode Ethernet MAC v7.0 core and it is configured to use the Configuration Vector, there is syntax that needs to be updated for the Verilog version of the core. Additional false path constraints are also needed to avoid the possibility of timing errors on asynchronous paths.

解决方案

1) In the Verilog core block level, the instantiation of the core has a syntax error.

The line:

      .bus2ip_addr  {12{1'b0}},

Should be changed to:

      .bus2ip_addr  ({12{1'b0}}),

2) In the core xdc file, you will need to add:

set_false_path -through [get_ports {rx_configuration_vector[*]}]
set_false_path -through [get_ports {tx_configuration_vector[*]}]

This has been addressed in the v7.0 (Rev1) update (Xilinx Answer 57446) and will also be addressed in the v8.0 core scheduled to be released in Vivado Design Suite 2013.3.

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