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  4. AR# 57208: 7 FPGA Gen3 Integrated Block for PCI Express v2.1 - 3DW TLP Header is Logged as 4DW TLP Header in the AER Header Log Register

AR# 57208

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7 FPGA Gen3 Integrated Block for PCI Express v2.1 - 3DW TLP Header is Logged as 4DW TLP Header in the AER Header Log Register

描述

Version Found: v2.1
Version Resolved and other Known Issues: See (Xilinx Answer 54645).

When TLP containing error is a 3DW Format/Type TLP, the core will always log 4DW TLP in the AER Header Log Register. For example:

  • Memory Read 3DW TLP + ECRC
    When this packet is logged into the AER, the Header Log register will show the 3DW Memory Read TLP header and 1DW of ECRC value.
  • Memory Write 3DW TLP + 1DW Payload + ECRC
    When this packet is logged into the AER, the Header Log register will show the 3DW Memory Write TLP Header and 1DW Payload data.

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

解决方案

There is currently no fix for this issue. However, the software (driver / user logic) can be designed to ignore the 4th DW if the first three DWs indicate that it is a 3DW Format/Type TLP packet.

Revision History
8/22/2013 - Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54645 Virtex-7 FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 57208
日期 10/28/2013
状态 Active
Type 综合文章
IP
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