This answer record contains the Release Notes and Known Issues for the Virtex-7 FPGA Gen3 Integrated Block for PCI Express Core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tool versions.
Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.
Xilinx PCI Express Cores Page:
https://www.xilinx.com/products/technology/pci-express.html
This article is part of the PCI Express Solution Centre
| (Xilinx Answer 34536) | Xilinx Solution Center for PCI Express |
General Information
For release notes on v1.7 of the Virtex-7 FPGA Gen3 Integrated Block for PCI Express core, see (Xilinx Answer 47441).
Supported devices can be found in the following three locations:
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v4.3 (Rev3) | 2018.3 |
| v4.3 (Rev3) | 2018.2 |
| v4.3 (Rev2) | 2018.1 |
| v4.3 (Rev1) | 2017.4 |
| v4.3 | 2017.3 |
| v4.2 (Rev5) | 2017.2 |
| v4.2 (Rev4) | 2017.1 |
| v4.2 (Rev3) | 2016.4 |
| v4.2 (Rev2) | 2016.3 |
| v4.2 (Rev1) | 2016.2 |
| v4.2 | 2016.1 |
| v4.1 (Rev1) | 2015.4 |
| v4.1 | 2015.3 |
| v4.0 (Rev1) | 2015.2 |
| v4.0 | 2015.1 |
| v3.0(Rev4) | 2014.4.1 |
| v3.0 (Rev4) | 2014.4 |
| v3.0 (Rev3) | 2014.3 |
| v3.0 (Rev2) | 2014.2 |
| v3.0 (Rev1) | 2014.1 |
| v3.0 | 2013.4 |
| v2.2 | 2013.3 |
| v2.1 | 2013.2 |
| v2.0 | 2013.1 |
| v1.4 | 2012.4 |
Design Advisory
| (Xilinx Answer 62296) | Design Advisory for 7 Series/Virtex-7 FGPA Gen3 Integrated Block for PCI Express / AXI Bridge for PCI Express (Vivado 2014.1/2014.2/2014.3) - Tool reports 'constant_clock' and 'unconstrained_internal_endpoints' when implementing core configured as Gen1 |
Tactical Patch
The following table provides a list of tactical patches for the Virtex-7 Gen3 Integrated Block Wrapper for PCI Express core, applicable to corresponding Vivado tool versions.
| Answer Record | Core Version (After installing the Patch) | Tool Version |
|---|---|---|
| (Xilinx Answer 64153) | v3.0 (Rev. 5) | 2014.4.1 |
| (Xilinx Answer 67111) | v4.2 (Rev. 67111) | 2016.1 |
Known and Resolved Issues
The following table provides known issues for the Virtex-7 FPGA Gen3 Integrated Block for PCI Express core, starting with v2.0, initially released in Vivado 2013.1.
Note: The "Version Found" column lists the version that the problem was first discovered in.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 65569) | Virtex-7 GTH QPLL temperature compensation attribute update | v4.2 (Rev1) | |
| (Xilinx Answer 67111) | Issue with MSI-X Table Offset | v4.2 | v4.2 (Rev1) |
| (Xilinx Answer 67172) | Example Design Simulation with VCS Simulator hangs indefinitely | v4.2 | Not Resolved Yet |
| (Xilinx Answer 65500) | Example Design Simulation with VCS Simulator Fails | v4.1 | v4.2 (Rev1) |
| (Xilinx Answer 64153) | PCIE_ASYNC_EN is not set correctly for Asynchronous Clocking | v3.0(Rev4) | v4.0 (Rev1) |
| (Xilinx Answer 62787) | Extended Tag Field Support | v3.0 (Rev3) | NA |
| (Xilinx Answer 62854) | Excessive BUFG usage | v3.0 (Rev3) | v3.0(Rev4) |
| (Xilinx Answer 60022) | TIMING-10#1 Warning Missing property on synchronizer | v3.0 (Rev1) | v3.0 (Rev2) |
| (Xilinx Answer 59900) | Post Synthesis/Implementation Netlist Functional/Timing Simulation Support | v3.0 (Rev1) | v4.0 |
| (Xilinx Answer 59899) | Resizable BAR Extended Capability Support | v3.0 | v3.0 (Rev2) |
| (Xilinx Answer 59961) | PCISIG Compliance Testing | v3.0 | v3.0 (Rev2) |
| (Xilinx Answer 59988) | Out of the box example design simulation fails with 'Address Aligned' mode for 256-bit AXI Interface and 64-bit BAR configuration | v3.0 | v3.0 (Rev2) |
| (Xilinx Answer 58723) | PIPE Simulation does not work with 250 MHz Reference Clock | v2.2 | v3.0(Rev1) |
| (Xilinx Answer 58271) | Legacy Interrupt Mode information in PG023 is not correct | v2.2 | v3.0 |
| (Xilinx Answer 58071) | Does not flag fatal error during completion buffer overflow | v2.2 | NA |
| (Xilinx Answer 56976) | PF1_SRIOV_FIRST_VF_OFFSET is incorrect | v2.1 | v3.0(Rev1) |
| (Xilinx Answer 56975) | Field to set "VF Device ID" in PF1 SRIOV Config tab of GUI is grayed out | v2.1 | v2.2 |
| (Xilinx Answer 54902) | IES/GES Device Support in Vivado 2013.1 and ISE Design Suite 14.5 | v2.0 | N/A |
| (Xilinx Answer 55309) | ERROR:Place:1340 - PAD.pci_exp_rxn<1> is tied to GTHE_CHANNEL.pcie3_7x_v1_4_i/inst/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[1] | v2.0 | v2.1 |
| (Xilinx Answer 53151) | Rate change back to Gen3 speed fails on x79 motherboard | v1.3 | NA |
| (Xilinx Answer 50837) | Some features in generated example design and testbench not verified | v1.2 | Not Resolved Yet |
| (Xilinx Answer 47604) | Incorrect Byte Count set when responding to Poisoned AtomicOp Request | v1.1 | NA |
Other Information:
| (Xilinx Answer 55085) | Virtex-7 Gen3 Integrated Block Wrapper for PCI Express v2.0 - Verilog Instantiation Changed from Uppercase to Lowercase |
| (Xilinx Answer 57342) | Virtex-7 FPGA Gen3 Integrated Block for PCI Express core SRIOV Example Design Simulation |
| (Xilinx Answer 58495) | Xilinx PCI Express Interrupt Debugging Guide |
| (Xilinx Answer 64632) | Virtex-7 FPGA Gen3 Integrated Block for PCI Express - How to enable 64 bit Prefetchable Memory Base/Limit Registers in TYPE1 Config Space? |
| (Xilinx Answer 57777) | COMMON_CFG Attribute update for Production Silicon |
| (Xilinx Answer 58076) | Virtex-7 FPGA Gen3 Integrated Block for PCI Express v2.2 - IES/GES devices support |
| (Xilinx Answer 57208) | 3DW TLP Header is Logged as 4DW TLP Header in the AER Header Log Register |
| (Xilinx Answer 58743) | How can I share the same clocking module between two PCIe cores? |
Revision History
| 04/03/2013 | Initial release |
| 06/19/2013 | Updated for 2013.2 |
| 08/04/2013 | Added (Xilinx Answer 56975) and (Xilinx Answer 56976) |
| 08/28/2013 | Added (Xilinx Answer 57208) |
| 10/03/2013 | Added (Xilinx Answer 57777) |
| 10/23/2013 | Updated for 2013.3 |
| 12/18/2013 | Updated for 2013.4 |
| 04/16/2014 | Updated for 2014.1 |
| 06/04/2014 | Updated for 2014.2 |
| 10/08/2014 | Updated for 2014.3 |
| 11/09/2014 | Added (Xilinx Answer 62296) |
| 11/24/2014 | Updated for 2014.4 release |
| 04/07/2015 | Added (Xilinx Answer 64153) |
| 04/15/2015 | Updated for 2015.1 release |
| 06/24/2015 | Updated for 2015.2 release |
| 10/06/2015 | Updated for 2015.3 release |
| 24/11/2015 | Updated for 2015.4 release |
| 04/13/2016 | Updated for 2016.1 release |
| 05/12/2016 | Added (Xilinx Answer 67172) |
| 06/06/2016 | Added (Xilinx Answer 67111) |
| 08/06/0216 | Updated for 2016.2 release |
| 07/05/2016 | Added (Xilinx Answer 65569) |
| 10/05/2016 | Updated for 2016.3 release |
| 01/24/2017 | Updated for 2016.4 release |
| 04/05/2017 | Updated for 2017.1 release |
| AR# 54645 | |
|---|---|
| 日期 | 08/26/2020 |
| 状态 | Active |
| Type | 版本说明 |
| IP | |