AR# 57436

描述

Version Found: All MIG 7 Series versions prior to 2.0 rev1
Version Resolved: MIG 7 Series v2.0 Rev1 (2013.3)

All versions of MIG 7 Series prior to v2.0 rev1 generate RDIMM single rank designs with one CS pin. As per the Jedec DDR3 standard, two CS pins are required for single rank RDIMM devices. The two CS pins are used for programming the SPD register.

With MIG 7 Series releases prior to v2.0 rev1, one CS pin is generated and the RDIMM SPD register is not being programmed. Therefore, the default SPD register programming is always used. In most cases, the default configuration is valid. However, for some RDIMM parts, the default programming is not valid and programming with both CS pins held low is necessary.

解决方案

For designs in production with MIG 7 Series revisions prior to 2.0 rev1:
If issues have not been seen, the single CS pin and default configuration of the SPD register is valid. However, it is important to ensure that the CS_n[1] pin not driven by MIG is not left floating or tied Low at the memory. If both CS_n pins drive Low, the SPD register will be reprogrammed. Please ensure CS_n[1] does not drive Low.

If issues have been seen due to the default programming of the SPD register, MIG 7 Series v2.0 rev1 is recommended or the manual work-around noted below can be used. MIG 2.0 rev1 (released with Vivado Design Suite 2013.3) will correctly generate the cs_n[1:0] pins and program the SPD register based on the RDIMM datasheet. The SPD register programming in 2013.3 will be functionally correct however, additional enhancements will be made in 2013.4 for optimization purposes. As an example, MIG 2.0 rev1 will always turn on all four of the clock outputs from the register, but in some cases only 1 or 2 are needed. 2013.4 will include this enhancement.

For designs not in production:
MIG 7 Series v2.0 rev1 should be used to generate RDIMM designs and two CS_n pins should be connected between the FPGA and the RDIMM.

Manual Updates to RTL:
1. Update the RC1 SPD register programming:
     -  Overwrite the generated user_design/rtl/phy/mig_7series_vx_x_ddr_phy_init.v module with the file attached to this answer record corresponding to the target MIG release in use.  These updated modules have the proper programming for the RC1 register.
        From:
             localparam REG_RC1 = 8'b00000001; // Current version where all the clocks are enabled
        To:
            localparam REG_RC1 = (RANKS <= 2) ? 8'b00110001 : 8'b00000001; // Older version where 0 and 3 clocks were enabled while disabling 1 and 2
2. For MIG 7 Series designs prior to v2.0, the voltage and temperature register settings should also be updated. See (Xilinx Answer 55525) for details.
     -  After completing step 1, add the following top-level parameters to the example_design/rtl/example_top.v and the user_design/rtl/core_name.v modules and pass the parameters through the MIG rtl hierarchy to the mig_7series_vx_x_ddr_phy_init.v module:
          - "DDR3_VDD_OP_VOLT"
              Set to 150 for DDR3 1.5V
              Set to 135 for DDR3L 1.35V
          - "VREF"
              Set to EXERNAL when Vref is supplied externally
              Set to INTERNAL when Vref is supplied internally
           - "tCK" 
               This is an existing parameter but needs to be mapped into the mig_7series_vx_x_ddr_phy_init.v module.
3. Add the cs_n[1] pin to the design.  
     - Modify the following parameters within the "example_design/rtl/example_top.v" and "user_design/rtl/core_name.v" files.  Note, these can be manually modified as noted below, or the target core can be generated in MIG 2.0 rev1 and the parameters copied to the older core version used:
          1. Change nCS_PER_RANK from 1 to 2.  Note, CS_WIDTH should not be modified; 1 is the correct setting.
          2. Modify the CS_MAP parameter to add the cs_n[1] location mapping.  Refer to UG586 Table 1-93 for information on setting CS_MAP.  
          3. Update the PHY_x_BITLANES parameter to include a 1 in the bit position of cs_n[1].  Refer to UG586 Table 1-93 for information on setting PHY_x_BITLANES.
     - Within the target XDC, add the cs_n[1] constraints.  The VCCAUX_IO, SLEW, IOSTANDARD, and pin LOC must be added.  For example,
            # PadFunction: IO_L16N_T2_38 
            set_property VCCAUX_IO NORMAL [get_ports {ddr3_cs_n[1]}]   
            set_property SLEW FAST [get_ports {ddr3_cs_n[1]}]
            set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[1]}]
            set_property LOC E18 [get_ports {ddr3_cs_n[1]}]
4.  If the cs_n[1] pin is added to an empty byte lane within the Address/Control bank, apply the following additional changes:
     - Apply all changes noted in step 3.
     - Modify the BYTE_LANES_Bx parameter within the "example_design/rtl/example_top.v" and "user_design/rtl/core_name.v" files. This parameter needs a 1 for the corresponding byte group that is being added.  Refer to UG586 Table 1-93 for information on setting BYTE_LANES_Bx.
     - Within the target XDC, add the OUT_FIFO and PHASER_OUT constraints for the newly added byte lane.

Note: The MIG 7 Series design includes invalid Register Control settings for RC3/4/5 when RDIMM has 8 or more loads; see (Xilinx Answer 57221). This is planned to be resolved in 2013.4.

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