AR# 58308

描述

FIFO Generator IP can generate an *_clocks.xdc file that uses the "set_max_delay -datapath_only" constraint, depending on the configuration of the FIFO chosen to constrain CDC (Clock Domain Crossing) paths that are associated with the FIFO logic.

User may add "set_clock_groups" constraint to relax timing on the two clocks associated with the FIFO in the user XDC file.

Because the "set_clock_groups" takes precedence over "set_max_delay", the FIFO "set_max_delay" constraints are not honored.

This does not show up in Vivado as an Error or Critical Warning since this conforms to constraint priority as defined by SDC.

How can I avoid this problem?

解决方案

To validate design constraints, run DRC with the "methodology_checks" rule deck in Synthesized design.

This problem can be captured with the "methodology_checks" rule deck with the following warning:

TIMING #1 Warning A set_clock_groups or a set_false path between clocks rdclk and wrclk overrides a set_max_delay -datapath_only (see constraint position 7 in the Timing Constraints window in Vivado IDE).

It is not recommended to override a "set_max_delay -datapath_only" constraint.

Below are some possible solutions:

1. The FIFO Generator uses point-to-point set_max_delay constraints.
   For the same XDC command, the more specific the objects in the constraint are, the higher priority the constraint is.
   So you can use set_max_delay between the two clock groups instead of set_clock_groups.
   In this way, the FIFO Generator set_max_delay constraints will take higher priority and will not be overridden.
   
   
2. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints.
   
   
3. Use the Built-in (or hardened) FIFO which does not require the "set_max_delay" constraints because the associated logic is hardened in silicon instead of in fabric.
   
   
4. Evaluate if the "set_max_delay" constraints can be safely ignored for a particular application.