AR# 58873

描述

MIG 7 Series includes specific trace matching requirements between CK/Addr, DQ/DQS and CK/DQS. 

The matching requirements are dependent on the target data rate, FPGA, and memory device and must include both PCB trace delay and package delay. 

To view the matching requirements (including derating values), please refer to the DDR3 Design Guidelines section within (UG586).

This answer record includes an automated checker to help with understanding the requirements for your specific system or for verifying previously laid out boards.

解决方案

Please use the attached 7Series_DDR3_PCB_Checker.xlsm and follow the steps below to generate the trace matching requirements.

Notes

1. This Checker only works on Windows.
2. Macros must be enabled in Excel.
3. The ISE or Vivado executable path must be defined in the environment variable "PATH".
4. Stripline is used for all signals. V=C * Sqr(Er) is used for fly-time on PCB. Here C = 3 E-10 cm/s.
5. In the FPGA Rating list, "HP/HR" is the bank type. "2.0/1.8" is the Vccaux_io power. "L" means an FBG package. For an FFG package use the options without "L".
6. In the FPGA Working mode list, "4:1/2:1" means memory/user clock ratio. "1.5V/1.35V" means DDR3 or DDR3L. "L" means the Vccint is 0.9V. For Vccint with 1.0V use the options without "L".
7. In the Design Flow list, "ISE" means ISE flow. "Vivado" means Vivado Flow. "Bypass" means no PKG file is generated. If "Bypass" is selected, the user should find all information.
8. When this check is used to get package delay automatically, all DDR3 signals must use the default MIG output signal name.
9. The UCF/XDC file MUST be MIG within the default output. Use "Board File" to select PCB layout length file.
10. If Board File is Select, the signal name of DDR3 MUST use default MIG signal name.
11. Adherence to Rule in the TotalDelay table means the length relationship between CK/Addr or DQS/DQ BEFORE PCB layout. This can help PCB layout constraint.
12. The current table can only support verification of address/control signals for one component. If other address/control skew is required, please enter new values for the new component.
13. The "Use DM" option is used when ECC is enabled and DM is ignored. "NO" means no DM is used.
    
14. The Board_File_Example sheet shows an example file format. The first column MUST be the signal name and the second column must be the route length.
    
15. A positive Adherence value means the signal should be longer than CK or DQS.  A negative value means the signal should be shorter than CK or DQS on board.
    
16. Zero in the Derating Table means that the value in the Overview option is not valid. 
17. Matching length for differential pins (CK/CK#, DQS/DQS#) is added for the adherence column. The differential I/O should be same length including flight time and route length.

How to use this tool:

1. Select all parameters in the tables. The value must be selected from the drop down list.
2. If no constraint or length file is selected, the checker will ignore it. The user should enter the value of the PCB route delay in the TotalDelay table.
3. Click the "Generate PKG" button. All signals will appear in the TotalDelay sheet.
4. After the command line shows that PKG or flight_time file is generated, click the "Open PKG" button to open PKG or the flight_time file and all information will show in the TotalDelay table.
5. If "No file selected" is selected for the constraint file and board file, enter the package delay and PCB route length in the TotalDelay table.
6. Click "Calculate Total Delay" and PCB route delay will show in ps. PCB route delay and package delay will be added to get the total delay.
7. Click the Verify button and the results will display. Reset will clear all contents for the next calculation.
8. If flight time information is generated, BYPASS should be selected for Design FLOW to regenerate the I/O list. If fly-time and board length are required, ISE/Vivado should be selected for FLOW to enable the tool to search for required information in the opened files.
   

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