2. 技术支持
  3. AR# 5965: 5.1i Timing, Constraint - PERIOD constraint analyzes path from a FROM:THRU:TO spec
  4. AR# 59654: 2013.4 Vivado - Controlling automatic BUFG insertion on reset nets during Vivado Implementation

AR# 59654

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2013.4 Vivado - Controlling automatic BUFG insertion on reset nets during Vivado Implementation

描述

The Vivado implementation flow will automatically insert BUFGs on reset nets that have a fanout of 50,000 and where there are not already 12 clock buffers (BUFG and BUFHCE) using global resources.

解决方案

These two thresholds can be modified with the following parameters:

To change the fannout  threshold from the default of 50000:

set_param logicopt.thresholdBUFGinsertHFN 20000 

To change the threshold of total BUFGs and instantiated BUFHCEs in the design:

set_param logicopt.thresholdBUFGperRegion 15

Note: the parameter name is misleading because the threshold is the total number.


AR# 59654
日期 06/19/2014
状态 Active
Type 综合文章
器件
Tools
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