描述
The following SystemVerilog code gives me an error in Vivado during Synthesis.
......
str.limit = str.match == str.din ? 4-1 : 3-1;
str.dout = 0;
for(int i=0;i<=str.limit;i=i+1)
begin
if(str.din[i])
begin
str.dout[i] = 1;
break;
end
end
Vivado Synthesis is not able to calculate the loop limit value from the dynamic variable and displays the following error message.
ERROR: [Synth 8-3380] loop condition does not converge after 2000 iterations [top.sv:38]