AR# 62786

描述

I have a synthesized design which can be opened without issue.

However, when I set the mark_debug attribute on a net in the synthesized design and reopen the synthesized design with the following steps, an error occurs.

Steps to add mark_debug attribute:

•   open project
•   open top.xdc
•   open synth_design
•   set_property mark_debug false [get_nets [list in_reg_third]]
•   save design
•   close design
•   refresh top.xdc
•   open synth_design

Error message:

  Parsing XDC File [xx/project_1.srcs/constrs_1/imports/src/top.xdc]
  Finished Parsing XDC File [xx/project_1.srcs/constrs_1/imports/src/top.xdc]
  ERROR: [Common 17-48] File not found: xx/project_1.ioplanning/constrs_1/designprops.xml

解决方案

This issue is fixed in Vivado 2014.3.

To work around this issue in Vivado 2014.2, you can export the DCP after setting the mark_debug attribute. 

The generated DCP can be used for ILA inserting and implementation.