When you instantiate a component in your design, the simulator must reference a library that describes the functionality of the component to ensure proper simulation.
The Xilinx libraries are divided into categories based on the function of the model.
You must specify different simulation libraries according to the simulation points.
This article describe the UNIFAST library for 7 Series in more detail.
The UNIFAST library is an optional library that you can use during RTL behavioral simulation to speed up simulation run time of a 7 Series design.
The simulation run time improvement is achieved by supporting a subset of the 7 Series primitive features in the simulation mode.
Please refer to each release of Vivado Design Suite User Guide: Logic Simulation (UG900) for a list of UNIFAST library models and their feature difference from the full models.
Note: The UNIFAST library cannot be used for sign-off simulations because the library components do not have all the checks/features that are available in a full model.
It is recommended to use the UNIFAST library for initial verification of the design and then run a complete verification using the UNISIM library.
VHDL UNIFAST Library
The VHDL UNIFAST library is located at <Vivado_Install_Dir>/data/vhdl/src/unifast.
The VHDL UNIFAST library has the same basic structure as Verilog and can be used with architectures or libraries.
You can include the library in the test bench file.
The following example uses a drill-down hierarchy with a for call:
Verilog UNIFAST Library
The Verilog UNIFAST library is located at <<Vivado_Install_Dir>/data/verilog/src/unifast.
There are two methods to use the Verilog UNIFAST library:
Method 1: Simulate all applicable models with the UNIFAST library (Recommended)
To enable UNIFAST support (fast simulation models) in a Vivado project environment for the Vivado simulator, ModelSim, IES, or VCS, check the <simulator>.elaborate.unifast checkbox in the Simulation Settings dialog box.
Starting in Vivado 2015.1, the <simulator>.elaborate.unifast option is deprecated. To enable UNIFAST support (fast simulation models) in a Vivado project environment for the Vivado simulator, ModelSim, IES, or VCS, use the following command in the Tcl console:
set_property unifast true [current_fileset simset]
Method 2: Simulate specific models with UNIFAST library (Advanced users)
To specify individual library components, Verilog configuration statements are used.
Specify the following in the config.v file:
Note: For ModelSim (vsim) only -genblk is added to the hierarchy name.
(For example: instance testbench.genblk1.inst.genblk1.O1 use unifast_ver.MMCME2;)
Example config.v
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 64053 | Xilinx Simulation Solution Center - Design Assistant - Simulation Libraries - UNIFAST | N/A | N/A |