2. 技术支持
  3. AR# 6517: 2.1i FPGA Editor - Selecting Virtex switch box pins sometimes highlights the pins next to them
  4. AR# 65177: Spartan-6 FPGA Integrated Endpoint Block for PCI Express - Release Notes

AR# 65177

|

Spartan-6 FPGA Integrated Endpoint Block for PCI Express - Release Notes

描述

This master answer record for Spartan-6 FPGA Integrated Endpoint Block for PCI Express core lists all release notes, Design Advisories, known issues and general information answer records for different versions of the core.

_________________________________________________
This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

解决方案

Release Notes:

(Xilinx Answer 32743) Release Notes: v1.1
(Xilinx Answer 33277) Release Notes: v1.2
(Xilinx Answer 35323) Release Notes: v1.3
(Xilinx Answer 37938) Release Notes: v1.4
(Xilinx Answer 37939) Release Notes: v2.1
(Xilinx Answer 39371) Release Notes: v2.2
(Xilinx Answer 42569) Release Notes: v2.3
(Xilinx Answer 45702) Release Notes: v2.4

Design Advisories:

(Xilinx Answer 33761) Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - How to enable use of a 100 MHz reference clock
(Xilinx Answer 33774) Design Advisory for the Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - 250 MHz Is Not a Valid Reference Clock Option

Known Issues/General Information:

(Xilinx Answer 33871) Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - Explanation of Engineering Sample Known Issues
(Xilinx Answer 37955) Spartan-6 FPGA Integrated Block for PCI Express - VHDL Wrapper Not Available for v2.1 Release
(Xilinx Answer 42339) Spartan-6 FPGA Integrated Block for PCI Express - What is the PMA_RX_CFG setting for an asynchronous link?
(Xilinx Answer 43576) Spartan-6 Integrated Block for PCI Express - Updated GTP Attributes for v1.4 core version
(Xilinx Answer 47200) Spartan-6 Integrated Block PCI Express - What is the minimum non-posted TLP buffer space required to throttle non-posted TLPs? Article
(Xilinx Answer 32867) Spartan-6 FPGA Integrated Block Wrapper v1.1 for PCI Express - Designs which use the cfg_pm_wake_n input to generate a PME event should implement a timeout counter
(Xilinx Answer 34615) Spartan-6 FPGA Integrated Block Wrapper for PCI Express - Patches and Wrapper Source Code Updates
(Xilinx Answer 35115) Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Transmitting memory writes eventually introduces corrupt payload
(Xilinx Answer 37595) Spartan-6 Integrated Block for PCI Express - SIM_DEVICE attribute on RAMB16BWER is not set to "SPARTAN6
(Xilinx Answer 37938) Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues
(Xilinx Answer 39063) Spartan-6 FPGA Integrated Block for PCI Express - Why does trn_reset_n/user_reset_out(AXI) assert after sys_reset_n asserts?
(Xilinx Answer 39548) Spartan-6 FPGA Integrated Block for PCI Express - Replay Timeout is occurring too fast when using VHDL wrapper
(Xilinx Answer 40626) Spartan-6 FPGA Integrated Block for PCI Express - DRC Error During Simulation using Provided Root Port Model
(Xilinx Answer 42454) Spartan-6 FPGA Integrated Block for PCI Express - CORE Generator GUI shows a value of 0 for bit 15 of the Device Capabilities Register
(Xilinx Answer 44442) Spartan-6 Integrated Block for PCI Express - AXI transmit packet is dropped due to L0s entry
(Xilinx Answer 45704) Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.4

AR# 65177
日期 02/01/2016
状态 Active
Type 综合文章
IP
People Also Viewed