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  4. AR# 65313: LogiCORE IP JESD204 PHY v2.0 - MMCM_Locked output port not generated for JESD PHY core generated with the "Shared Logic in Core" option

AR# 65313

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LogiCORE IP JESD204 PHY v2.0 - MMCM_Locked output port not generated for JESD PHY core generated with the "Shared Logic in Core" option

描述

I am using the LogiCORE IP JESD204 PHY v2.0 (2015.1).

If the JESD PHY core is generated for an Artix-7 device in IPI with the "Shared Logic in Core" option selected, mmcm_reset and mmcm_lock pins are missing from the generated core.

解决方案

To work around this limitation with the "Shared Logic in Core" option selected, use the clocking wizard and connect the mmcm reset out of the second PHY core with Shared Logic in the Example Design.

Connect the locked output from the clocking wizard to the mmcm_lock pin.

The clocking module of the PHY with "Shared Logic in Core" can be checked for settings and connections of the mmcm.

The description of mmcm_lock is added to JESD204 PHY v3.0 LogiCORE IP Product Guide.

This is resolved in JESD204 PHY v3.0 (Vivado 2015.3).

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
61911 LogiCORE IP JESD204 PHY core - Release Notes and Known Issues N/A N/A
AR# 65313
日期 09/03/2015
状态 Active
Type 综合文章
IP
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