This answer record contains the Release Notes and Known Issues for the LogiCORE IP JESD204 PHY core and includes the following:
This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2014.3 and newer tools.
For Known Issues with the JESD204 LogiCORE IP, please visit
| (Xilinx Answer 44405) | LogiCORE IP JESD204 - Release Notes and Known Issues |
Or
| (Xilinx Answer 54480) | LogiCORE IP JESD204B - Release Notes and Known Issues for Vivado 2013.1 and newer tools. |
For Known Issues with the JESD204C LogiCORE IP, please visit
(Xilinx Answer 68804) LogiCORE IP JESD204C - Release Notes and Known Issues
JESD204 LogiCORE IP Page:
https://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-jesd204.html
Xilinx Forums:
Please seek technical support via the Networking and Connectivity Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
General Information
Supported devices can be found in the following three locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
Alternatively, see the Change Log Answer Records:
| Answer Record | Title |
|---|---|
| (Xilinx Answer 73626) | 2020.1 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 72923) | 2019.2 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 72242) | 2019.1 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 71806) | 2018.3 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 71212) | 2018.2 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 70699) | 2018.1 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 70386) | 2017.4 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 69903) | 2017.3 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 69326) | 2017.2 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 69055) | 2017.1 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 68369) | 2016.4 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 68021) | 2016.3 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 67345) | 2016.2 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 66930) | 2016.1 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 66004) | 2015.4 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 65570) | 2015.3 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 65077) | 2015.2 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 64619) | 2015.1 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 63724) | 2014.4.1 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 62882) | 2014.4 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 62144) | 2014.3 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 61087) | 2014.2 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 59986) | 2014.1 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 58670) | 2013.4 Vivado IP Release Notes - All IP Change Log Information |
| (Xilinx Answer 58605) | 2013.3 Vivado IP Release Notes - All IP Change Log Information |
For any Transceiver related questions or issue, please see the table below.
| Answer Record | Title |
|---|---|
| (Xilinx Answer 41613) | 7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List |
| (Xilinx Answer 57487) | UltraScale FPGA Transceiver Wizard - Release Notes and Known Issues for Vivado 2013.4 and newer versions |
| (Xilinx Answer 62670) | UltraScale FPGAs GTH Transceiver - Known Issues and Answer Record List |
| (Xilinx Answer 64440) | UltraScale FPGA GTY Transceiver - Known Issues and Answer Record List |
| (Xilinx Answer 64838) | Design Advisory for UltraScale FPGA Transceivers Wizard: GTH Production Updates in Vivado 2015.2 |
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version |
|---|---|
| v4.0(Rev. 8) | 2020.1 |
| v4.0(Rev. 7) | 2019.2 |
| v4.0(Rev. 6) | 2019.1 |
| v4.0(Rev. 4) | 2018.3 |
| v4.0(Rev. 3) | 2018.2 |
| v4.0(Rev. 2) | 2018.1 |
| v4.0(Rev. 1) | 2017.4 |
| v4.0 | 2017.3 |
| v3.4 | 2017.2 |
| v3.3 | 2017.1 |
| v3.2 (Rev. 1) | 2016.4 |
| v3.2 | 2016.3 |
| v3.1 (Rev. 1) | 2016.2 |
| v3.1 | 2016.1 |
| v3.0 | 2015.4 |
| v2.0(Rev. 2) | 2015.3 |
| v2.0 (Rev. 1) | 2015.2 |
| v2.0 | 2015.1 |
| v1.0 (Rev. 2) | 2014.4.1 |
| v1.0 (Rev. 1) | 2014.4 |
| v1.0 | 2014.3 |
Known and Resolved Issues
The following table provides known issues for the LogiCORE IP JESD204 PHY core, starting with v1.0, initially released in Vivado 2014.3.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 63634) | LogiCORE IP JESD204 PHY v1.0 - TX_RESET_GT and RX_RESET_GT affect both TX and RX SERDES | v1.0 | v2.0 |
| (Xilinx Answer 64749) | LogiCORE IP JESD204 PHY v2.0 - CPLLPD not correctly set | v2.0 | v2.0 (Rev. 1) |
| (Xilinx Answer 65313) | LogiCORE IP JESD204 PHY v2.0 - MMCM_Locked output port not generated for JESD PHY core generated with Shared Logic in Core option | v2.0 | v3.0 |
| (Xilinx Answer 65479) | JESD204B - Single Lane JESD204 Transmit Example Design Simulations Timing Out When Using QuestaSim | ||
| (Xilinx Answer 66029) | LogiCORE IP JESD204 PHY v3.0 - Core fails to generate UltraScale Transceiver with correct settings for some configurations | v3.0 | v3.1 |
| (Xilinx Answer 66575) | JESD204 and JESD204 PHY - Multi-lane JESD interfaces and the rxencommaalign signal | ||
| (Xilinx Answer 66576) | JESD204 - Clock stability | ||
| (Xilinx Answer 67043) | JESD204 v7.0 and JESD204_PHY v3.1 - 2016.1 - Defaults to DFE Equalization mode | v3.1 (Rev. 1) | |
| (Xilinx Answer 67044) | JESD204 PHY v2.0, v3.0, v3.1 (2015.1, 2015.2, 2015.3, 2015.4, 2016.1) - TXDIFFCTRL low default value | v3.1 (Rev. 1) | |
| (Xilinx Answer 67354) | JESD204 PHY - CPLLPD is not held high for at least 2us | v3.2 | |
| (Xilinx Answer 69021) | JESD204 - 2017.1 - UltraScale / UltraScale+ IBUFDS_GTE output instability | ||
| (Xilinx Answer 69027) | JESD204 - Single Lane JESD204 Transmit Example Design simulations timing out when using QuestaSim | ||
| (Xilinx Answer 69508) | JESD204 PHY (v3.1) - RXLPMEN values incorrect when neither AXI-Lite nor Transceiver Debug are enabled | v3.1 | v4.0 |
| (Xilinx Answer 69510) | JESD204 PHY (v2.0) - CPLL_PD values incorrect when AXI-Lite is not enabled | v2.0 | v4.0 |
| (Xilinx Answer 69522) | JESD204 PHY (v3.4) - txoutclk / rxoutclk clocks not running | v3.4 | v4.0 |
| (Xilinx Answer 70023) | JESD204 PHY (v3.4, v4.0) - When using CPLL_CAL block included CPLLPD is not held high for at least 2us | v3.4 | v4.0 (Rev. 1) |
| (Xilinx Answer 71154) | JESD204 PHY v4.0 - The JESD204_PHY core txoutclk and rxoutclk pins do not have the correct frequency property set in IP Integrator when you enter an integer number as the line rate in the IP GUI | v4.0(Rev. 2) | v4.0 (Rev. 2) |
Revision History
| 06/15/2016 | Added (Xilinx Answer 72242), (Xilinx Answer 72923), (Xilinx Answer 73626), Updated for 2019.1, 2019.2 and 2020.1 release |
| 12/13/2018 | Updated for 2018.3 |
| 11/02/2018 | Added (Xilinx Answer 71154) |
| 11/06/2017 | Added (Xilinx Answer 70023) |
| 10/10/2017 | Updated for 2017.2 |
| 09/29/2017 | Added (Xilinx Answer 69522) |
| 07/24/2017 | Added (Xilinx Answer 69508); (Xilinx Answer 69510) |
| 04/11/2017 | Updated for 2017.1 |
| 03/14/2017 | Updated for 2016.3 and 2016.4 |
| 11/25/2016 | Added (Xilinx Answer 67354) |
| 06/10/2016 | Added (Xilinx Answer 67345) |
| 05/11/2016 | Added (Xilinx Answer 67043), (Xilinx Answer 67044), (Xilinx Answer 66930) |
| 02/09/2016 | Added (Xilinx Answer 66576) |
| 02/09/2016 | Added (Xilinx Answer 66575) |
| 12/10/2015 | Added (Xilinx Answer 66004) |
| 11/26/2015 | Added (Xilinx Answer 66029) |
| 09/01/2015 | Added (Xilinx Answer 65313) |
| 08/28/2015 | Updated for 2015.2 release. Added (Xilinx Answer 65077). |
| 07/03/2015 | Added (Xilinx Answer 64838) |
| 06/12/2015 | Added (Xilinx Answer 64749) |
| 06/04/2015 | Updated for 2015.1 release. Added (Xilinx Answer 62670) and (Xilinx Answer 64440) |
| 02/19/2014 | Added (Xilinx Answer 63640) |
| 01/20/2014 | Updated for 2014.4 release |
| 10/07/2014 | Initial Release |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 67698 | JESD204 Solution Center - Top Issues and Frequently Asked Questions | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 64838 | UltraScale FPGA 收发器向导的设计咨询：Vivado 2015.2 中的 GTH 生产更新 | N/A | N/A |