AR# 66223

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Zynq UltraScale+ MPSoC Processing System IP - Incorrect DRC with default configuration for DDR

描述

In the Processor Configuration Wizard on the DDR configuration page, if I change the type from DDR4 to DDR3 a DRC is displayed with default values.

解决方案

Please refer to the DRC errors and resolve them manually as suggested.

For Example: Set the DDR clock frequency to 400 MHz from 800 MHz as it would be out of range and so on.

This is expected to be fixed in the 2016.1 release.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
66183 Zynq UltraScale+ MPSoC 处理系统 IP - 发布说明和已知问题 N/A N/A
AR# 66223
日期 12/29/2015
状态 Active
Type 综合文章
器件
Tools
IP
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