This Answer Record contains a comprehensive list of IP cchange log information from Vivado 2016.1 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.
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10G Ethernet MAC (15.1)
* Version 15.1
* Fixed corner case RX issue - Frames with bad CRC were not dropped when the frame's composition matched a certain pattern
* Fixed RX Issue - Frames, which had L/T field indicating length, were not dropped if the L/T field did not match the actual packet length
* Fixed RX Stats Issue - RX Statistics bit 29 is not asserted for frames which had L/T field indicating length when the L/T field was incorrect
* Added new feature - Link Interruption detection
* Fixed corner case TX issue - Error codes were not transmitted when implicit error and frame oversize error events occur at the same time
* Fixed bugs in 64-bit Example design FIFO which caused frames to be dropped
* Changes to HDL library management to support Vivado IP simulation library
10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)
* Version 6.0 (Rev. 4)
* Registering of combinatorial resets before passing it to GT Wizard
* Getting loopback signal to top
* Fixing resetting of PCS and PMA loopback in MDIO
* Removing support for UltraScale plus devices for this product line
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
10G Ethernet Subsystem (3.1)
* Version 3.1
* Added new feature - Link Interruption detection
* Refer to ten_gig_eth_mac_v15_1 and ten_gig_eth_pcs_pma_v6_0 core change logs for changes in the sub cores of this core
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
10G/25G Ethernet Subsystem (1.2)
* Version 1.2
* Re-Enabled 3 and 4 cores for 25G
* 1588 1-step and 2-step support added for MAC/PCS-PMA only
* Support added for GTH for 10G
* Runtime Switchable support added
* Added RS-FEC support for 25G
* Added -1HV support with 25G data rate
* Added support for Kintex UltraScale, Kintex UltraScale Plus and Zynq UltraScale Plus
* Timing closure may be difficult for 3 and 4 core with AN/LT enabled, see AR66787 for more information
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
1G/2.5G Ethernet PCS/PMA or SGMII (15.2)
* Version 15.2
* Adding GTYE3 and GTYE4 support.
* Adding selection option for GTH and GTY transceivers for UltraScale and UltraScale+ devices.
* Added support for Virtex UltraScale+ devices.
* Added support to interface with GEM of Zynq UltraScale+ devices.
* Added support for GT in example design for UltraScale and UltraScale+ devices.
* Added support for Rx GMII interface to work at RXOUTCLK.
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
32-bit Initiator/Target for PCI (7-Series) (5.0)
* Version 5.0 (Rev. 8)
* Fixed issue with is_eval constant declaration. No functional changes.
3GPP LTE Channel Estimator (2.0)
* Version 2.0 (Rev. 11)
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
3GPP LTE MIMO Decoder (3.0)
* Version 3.0 (Rev. 11)
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
3GPP LTE MIMO Encoder (4.0)
* Version 4.0 (Rev. 10)
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
3GPP Mixed Mode Turbo Decoder (2.0)
* Version 2.0 (Rev. 11)
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
3GPP Turbo Encoder (5.0)
* Version 5.0 (Rev. 10)
* Corrected CE signal name case in IP-XACT port description
* Revision change in one or more subcores
3GPPLTE Turbo Encoder (4.0)
* Version 4.0 (Rev. 10)
* Corrected CE signal name case in IP-XACT port description
* Revision change in one or more subcores
40G/50G Ethernet Subsystem (1.0)
* Version 1.0
* MAC + PCS and PCS only support for 40G and 50G
* Base-KR and Base-R support
* FEC, AN/LT and PTP 1588v2 support
* Support for Virtex UltraScale and UltraScale PLUS
* Changes to HDL library management to support Vivado IP simulation library
64-bit Initiator/Target for PCI (7-Series) (5.0)
* Version 5.0 (Rev. 8)
* Fixed issue with is_eval constant declaration. No functional changes.
7 Series FPGAs Transceivers Wizard (3.6)
* Version 3.6 (Rev. 2)
* RX_CM_TRIM attribute for Display Port Preset updated for GTH and GTP transceiver based devices
* ACCLK_TERM_EN_0 and ACCLK_TERM_EN_1 updated for GTZ transceiver based devices as per latest UG478
7 Series Integrated Block for PCI Express (3.3)
* Version 3.3
* Modified the width of pipe_tx_*_sigs, common_commands_in and common_commands_out
* Added Tandem support for xc7z035
* Modified the mapping of logical and physical external pipe interface ports for End Point configurations so that it can be connected to Root Port instance directly
* Fixed issue with the default values of 'Base Class Menu' and 'Sub Class Interface Menu' and 'Class Code' update when Lookup Assistant option is used
* Removed the dependency of 'Include Shared Logic(clocking)in example design' on 'External PIPE Interface' pipe mode simulation option. No changes made to the 'Enable Pipe mode Simulation' option
* Revision change in one or more subcores
AHB-Lite to AXI Bridge (3.0)
* Version 3.0 (Rev. 6)
* Updated example design subcore version. No functional changes
AXI 1G/2.5G Ethernet Subsystem (7.0)
* Version 7.0 (Rev. 4)
* Support GTY
* Revision change in one or more subcores
AXI AHBLite Bridge (3.0)
* Version 3.0 (Rev. 6)
* Updated example design subcore version. No functional changes
AXI APB Bridge (3.0)
* Version 3.0 (Rev. 6)
* Updated example design subcore version. No functional changes
AXI BFM Cores (5.0)
* Version 5.0 (Rev. 7)
* No changes
AXI BRAM Controller (4.0)
* Version 4.0 (Rev. 7)
* Minimum depth allowed is changed to 512 for IPI designs, in case depth is less than 512 it will be reset to 512
* Revision change in one or more subcores
AXI Bridge for PCI Express Gen3 Subsystem (2.1)
* Version 2.1
* Added Tandem and MCAP support for UltraScale configuration of the core.
* Modified the width of pipe_tx_*_sigs, common_commands_in and common_commands_out
* Modified the mapping of logical and physical external pipe interface ports for EP configurations so that it can be connected to Root Port instance directly
* Changes to HDL library management to support Vivado IP simulation library
* Fixed issue with the default values of 'Base Class Menu' and 'Sub Class Interface Menu'
* Added support for defense grade Kintex UltraScale devices - xqku040-rfa1156,xqku040-rba676,xqku060-rfa1156 and xqku095-rfa1156
* Added port msix_entry_num input for future use of internal MSI-X table implementation; currently it is always disabled
* Port width for s_axi_ctl_awaddr and s_axi_ctl_araddr is changed depending on device port type selection. EP is limited to 4K and RP is limited to 256M
* Added axi_ctl_aresetn output signal to allow access to S_AXI_CTL interface when there's no link-up
* pcie3_cfg_msix interface is accessible only when external MSI-X table implementation is selected; currently only external implementation is supported
* Added the required Tandem and MCAP ports: cap_*, startup_*, mcap_*
* Added HAS_BURST parameter on M_AXI interfaces for SmartConnect optimization
* Added two new ports to transceiver debug interface section: gt_dmonfiforeset gt_dmonitorclk.
* Revision change in one or more subcores
AXI CAN (5.0)
* Version 5.0 (Rev. 11)
* Updated example design subcore version. No functional changes
* Revision change in one or more subcores
AXI Central Direct Memory Access (4.1)
* Version 4.1 (Rev. 8)
* Updated example design subcore version. No functional changes
* Revision change in one or more subcores
AXI Chip2Chip Bridge (4.2)
* Version 4.2 (Rev. 8)
* Aurora_8b10b single lane support added for 32-bit configuration
* Helper core version fifo_generator_v13_1 update and safety circuit enablement for safe fifo reset operation. No other functional changes.
* Revision change in one or more subcores
AXI Clock Converter (2.1)
* Version 2.1 (Rev. 7)
* Sub core IP clk_wiz version changed to 5.3
* Update to fifo_generator 13.1
* Revision change in one or more subcores
AXI Crossbar (2.1)
* Version 2.1 (Rev. 9)
* Sub core IP clk_wiz version changed to 5.3
* IP Customization improvement for ADDR_WIDTH property in AXI4LITE mode
* Revision change in one or more subcores
AXI Data FIFO (2.1)
* Version 2.1 (Rev. 7)
* Sub core IP clk_wiz version changed to 5.3
* Updated to use FIFO Generator v13.1
* Revision change in one or more subcores
AXI Data Width Converter (2.1)
* Version 2.1 (Rev. 8)
* Sub core IP clk_wiz version changed to 5.3
* Update to use FIFO Generator v13.1
* Revision change in one or more subcores
AXI DataMover (5.1)
* Version 5.1 (Rev. 10)
* Updated example design subcore version. No functional changes
* Revision change in one or more subcores
AXI Direct Memory Access (7.1)
* Version 7.1 (Rev. 9)
* Updated example design subcore version. No functional changes
* Revision change in one or more subcores
AXI EMC (3.0)
* Version 3.0 (Rev. 8)
* Constraints updated to improve timing
* Revision change in one or more subcores
AXI EPC (2.0)
* Version 2.0 (Rev. 11)
* Updated example design subcore version. No functional changes
* Revision change in one or more subcores
AXI Ethernet Buffer (2.0)
* Version 2.0 (Rev. 11)
* Revision change in one or more subcores
AXI Ethernet Clocking (2.0)
* Version 2.0 (Rev. 2)
* No changes
AXI Ethernet Lite (3.0)
* Version 3.0 (Rev. 6)
* Adopted inference based memory in place of memory generator. No Impact of customer designs expected
* Revision change in one or more subcores
AXI GPIO (2.0)
* Version 2.0 (Rev. 10)
* Updated example design subcore version. No functional changes
* Revision change in one or more subcores
AXI HWICAP (3.0)
* Version 3.0 (Rev. 12)
* Updated example design subcore version. No functional changes
* Revision change in one or more subcores
AXI IIC (2.0)
* Version 2.0 (Rev. 11)
* Fixed RTL to maintain bus free time between STOP and START condition (applicable when first master generates STOP and subsequently second master generates START). In this case also, value programed in TBUF register is used to wait before generating START after STOP
* Updated example design subcore version
* Revision change in one or more subcores
AXI Interconnect (2.1)
* Version 2.1 (Rev. 9)
* Added user parameters Sxx_ARB_PRIORITY to allow assignment of arbiter priority in first tier crossbar when advanced options are enabled.
* Revision change in one or more subcores
AXI Interrupt Controller (4.1)
* Version 4.1 (Rev. 6)
* Added Cascade Interrupt Mode bus interface to simplify cascade mode connections
* Improved Cascade Interrupt Mode configuration checks
* Allow selection of single interrupt output bus interface
AXI Lite IPIF (3.0)
* Version 3.0 (Rev. 3)
* No changes
AXI MMU (2.1)
* Version 2.1 (Rev. 6)
* Sub core IP clk_wiz version changed to 5.3
* Revision change in one or more subcores
AXI Master Burst (2.0)
* Version 2.0 (Rev. 7)
* No changes
AXI Memory Mapped To PCI Express (2.8)
* Version 2.8
* Modified the width of pipe_tx_*_sigs, common_commands_in and common_commands_out
* Changes to HDL library management to support Vivado IP simulation library
* Added HAS_BURST parameter on M_AXI interfaces for SmartConnect optimization
* Revision change in one or more subcores
AXI Memory Mapped to Stream Mapper (1.1)
* Version 1.1 (Rev. 7)
* Revision change in one or more subcores
AXI Performance Monitor (5.0)
* Version 5.0 (Rev. 10)
* Updated IP RTL to consider narrow read transactions for read byte metric calculations
* Revision change in one or more subcores
AXI Protocol Checker (1.1)
* Version 1.1 (Rev. 9)
* Sub core IP clk_wiz version changed to 5.3
* Revision change in one or more subcores
AXI Protocol Converter (2.1)
* Version 2.1 (Rev. 8)
* Sub core IP clk_wiz version changed to 5.3
* Revision change in one or more subcores
AXI Quad SPI (3.2)
* Version 3.2 (Rev. 7)
* Core fileset changed from VHDL language only to Any language
* No Functional changes.
* Revision change in one or more subcores
AXI Register Slice (2.1)
* Version 2.1 (Rev. 8)
* Sub core IP clk_wiz version changed to 5.3
* Revision change in one or more subcores
AXI TFT Controller (2.0)
* Version 2.0 (Rev. 12)
* Updated example design subcore version. No functional changes
* Revision change in one or more subcores
AXI Timebase Watchdog Timer (3.0)
* Version 3.0
* Window Watch Dog Timer feature is added ,example design updated for the same
* Revision change in one or more subcores
AXI Timer (2.0)
* Version 2.0 (Rev. 10)
* Updated example design subcore version. No functional changes
* Revision change in one or more subcores
AXI Traffic Generator (2.0)
* Version 2.0 (Rev. 9)
* Added GUI options to control the Random Address in AXI mode and Random Data in AXI-Streaming mode
* Added Multi cycle constraints in AXI4 Advanced mode to improve timing
* Revision change in one or more subcores
AXI UART16550 (2.0)
* Version 2.0 (Rev. 10)
* Updated RTL to remove unnecessary de-assertion of Interrupt port on write to THR
* Updated example design subcore version
* Revision change in one or more subcores
AXI USB2 Device (5.0)
* Version 5.0 (Rev. 9)
* Helper core version update (clk_wiz_v5_3).
* RTL updated to fix 64bit register read
* Revision change in one or more subcores
AXI Uartlite (2.0)
* Version 2.0 (Rev. 12)
* Updated example design subcore version. No functional changes
* Revision change in one or more subcores
AXI Video Direct Memory Access (6.2)
* Version 6.2 (Rev. 7)
* Updated example design subcore version. No functional changes
* Adopted inference based memory in place of memory generator for IP. No Impact on customer designs.
* Revision change in one or more subcores
AXI Virtual FIFO Controller (2.0)
* Version 2.0 (Rev. 10)
* Simulation file set updated to support mixed language
* Revision change in one or more subcores
AXI-Stream FIFO (4.1)
* Version 4.1 (Rev. 5)
* Revision change in one or more subcores
AXI4-Stream Accelerator Adapter (2.1)
* Version 2.1 (Rev. 7)
* Renamed internal cdc_sync entity name. No functional changes
* Revision change in one or more subcores
AXI4-Stream Broadcaster (1.1)
* Version 1.1 (Rev. 8)
* Repackaged IP to improve internal automation. No functional changes.
* Simulation library change for dynamic source files and reduced file name length.
* Revision change in one or more subcores
AXI4-Stream Clock Converter (1.1)
* Version 1.1 (Rev. 9)
* Updated XDC in sync with fifo changes
* Synchronize to FIFO Generator v13.1
* Revision change in one or more subcores
AXI4-Stream Combiner (1.1)
* Version 1.1 (Rev. 7)
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
AXI4-Stream Data FIFO (1.1)
* Version 1.1 (Rev. 9)
* Updated XDC in sync with FIFO changes
* Updated to use FIFO Generator v13.1
* Revision change in one or more subcores
AXI4-Stream Data Width Converter (1.1)
* Version 1.1 (Rev. 7)
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
AXI4-Stream Interconnect (2.1)
* Version 2.1 (Rev. 9)
* Update IP integrator automation to avoid ambiguous Tcl command scenario.
* Revision change in one or more subcores
AXI4-Stream Protocol Checker (1.1)
* Version 1.1 (Rev. 8)
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
AXI4-Stream Register Slice (1.1)
* Version 1.1 (Rev. 8)
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
AXI4-Stream Subset Converter (1.1)
* Version 1.1 (Rev. 8)
* Simulation library change for dynamic source files and reduced file name length.
* Revision change in one or more subcores
AXI4-Stream Switch (1.1)
* Version 1.1 (Rev. 8)
* Implemented xpm_cdc libs for concise MTBF/constraints.
* Revision change in one or more subcores
AXI4-Stream to Video Out (4.0)
* Version 4.0 (Rev. 2)
* Supported devices and production status are now determined automatically, to simplify support for future devices
* Revision change in one or more subcores
Accumulator (12.0)
* Version 12.0 (Rev. 9)
* Revision change in one or more subcores
Adder/Subtracter (12.0)
* Version 12.0 (Rev. 9)
* GUI bug fix to disable SSET and SINIT controls for pipelined fabric implementations as these options were never supported.
* Revision change in one or more subcores
Aurora 64B66B (11.1)
* Version 11.1
* Improved Performance and Utilization for GTY designs in Framing mode
* Added feature to preview shared logic files when Shared logic in Example Design option is selected
* Removed the dependency on gtwiz_reset_rx_cdr_stable_out from GT channel to re-initialize the core for UltraScale Devices
* Added gt_rxusrclk_out optional port when Additional transceiver control and status ports option is enabled
* Revision change in one or more subcores
Aurora 8B10B (11.0)
* Version 11.0 (Rev. 4)
* Fixed preserving Equalizer selection issue when additional transceiver ports option is enabled
* Adjusted line rate and associated frequency limits for -1,-1H,1HV,-1L,-1LV, -2LV speed grade devices to match UltraScale FPGAs Data Sheet
* Revision change in one or more subcores
Binary Counter (12.0)
* Version 12.0 (Rev. 9)
* Revision change in one or more subcores
Block Memory Generator (8.3)
* Version 8.3 (Rev. 2)
* Updated the IP to deliver only Verilog behavioral model
* Updated the IP to support UltraRAM in IP Integrator
* Updated the IP to support the device package changes
CANFD (1.0)
* Version 1.0 (Rev. 1)
* Core XDC updated as per subcore changes
* Adopted inference based memory in place of memory generator. No Impact of customer designs expected
* Updated example design subcore version
* Revision change in one or more subcores
CIC Compiler (4.0)
* Version 4.0 (Rev. 10)
* Revision change in one or more subcores
CORDIC (6.0)
* Version 6.0 (Rev. 10)
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
CPRI (8.6)
* Version 8.6
* Updated to support version 7.0 of the CPRI specification without FEC.
* Added 24.33024Gbps line rate support using 64-bit datapath for Virtex UltraScale devices (GTYE3 transceivers).
* Added 10.1376Gbps, 9.8304Gbps and lower support to 12.16512Gbps capable GTHE3 based cores.
* Added 12.16512Gbps and 8.11008Gbps support to GTHE2 based cores.
* Added 12.16512Gbps support to GTXE2 based cores.
* Added fix for ports gt0_rxnotintable & gt0_rxdisperr which had incorrect bus widths with Artix7 devices.
* Corrected ordering of sync header in 64b66b cores.
* Corrected polarity of BUFG_GT CLRMASK port drivers in clocking logic.
* Changes to HDL library management to support Vivado IP simulation library
* Added debug signals register.
* Increased resolution of CDC FIFO delay reporting.
* Reduced frequency of recclk_out in example design to improve timing.
* Revision change in one or more subcores
Chroma Resampler (4.0)
* Version 4.0 (Rev. 8)
* Changed Virtex UltraScale family status to production.
* Revision change in one or more subcores
Clocking Wizard (5.3)
* Version 5.3
* Added Clock Monitor Feature as part of clocking wizard
* DRP registers can be directly written through AXI without resource utilization
* Changes to HDL library management to support Vivado IP simulation library
Color Correction Matrix (6.0)
* Version 6.0 (Rev. 9)
* Revision change in one or more subcores
Color Filter Array Interpolation (7.0)
* Version 7.0 (Rev. 8)
* Changed Virtex UltraScale family status to production.
* Revision change in one or more subcores
Complex Multiplier (6.0)
* Version 6.0 (Rev. 11)
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
Convolution Encoder (9.0)
* Version 9.0 (Rev. 10)
* Revision change in one or more subcores
DDR3 SDRAM (MIG) (1.2)
* Version 1.2
* Updated for 2016.1
* Resolved issues related to certain speed grades incorrectly preventing previously allowed input clock periods. See Xilinx Answer 62543 for details.
* Resolved issues related to tIS memory model violations on ADDR and BA occur when simulating DDR3 example_tb testbench. See (Xilinx Answer 65421) for details.
* Revision change in one or more subcores
DDR4 SDRAM (MIG) (2.0)
* Version 2.0
* Updated for 2016.1
* Resolved issues related to certain speed grades incorrectly preventing previously allowed input clock periods. See Xilinx Answer 62543 for details.
* Added DBI (Data Bus Inversion) Support
* Revision change in one or more subcores
DDS Compiler (6.0)
* Version 6.0 (Rev. 12)
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
DMA Subsystem for PCI Express (PCIe) (2.0)
* Version 2.0
* Modified the width of pipe_tx_*_sigs, common_commands_in and common_commands_out
* Modified the mapping of logical and physical external pipe interface ports for End Point configurations so that it can be connected to Root Port device directly
* Changes to HDL library management to support Vivado IP simulation library
* Added Tandem and MCAP support for UltraScale configuration of the core.
* Removed m_axis_h2c_tkeep_0/1/2/3 signals
* Added option to disable pcie_cfg_mgmt interface depending on the parameter Configuration Management Interface
* Added support for defense grade Kintex UltraScale devices - xqku040-rfa1156,xqku040-rba676,xqku060-rfa1156 and xqku095-rfa1156
* Added bus interfaces for dsc_bypass_c2h_* and dsc_bypass_h2c_* signals for all the 4 channels
* Added interface dma_status_ports for c2h_sts_* and h2c_sts_* signals
* Fixed issue with the default values of 'Base_Class_Menu' and 'Sub Class_Interface_Menu'
* Added the required Tandem and MCAP ports: cap_*, startup_*, mcap_* interfaces
* Added HAS_BURST parameter on M_AXI interfaces for SmartConnect optimization
* Added two new ports to transceiver debug interface section: gt_dmonfiforeset gt_dmonitorclk.
* Revision change in one or more subcores
DSP48 Macro (3.0)
* Version 3.0 (Rev. 12)
* Revision change in one or more subcores
DUC/DDC Compiler (3.0)
* Version 3.0 (Rev. 10)
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
Debug Bridge (1.0)
* Version 1.0
* Native Vivado Release
Decapsulator (1.0)
* Version 1.0
* Initial release
* Feature support in accepting Ethernet packets and performs header stripping (output RTP packets), channel matching and filtering, video stream detection and video frame boundary alignment
Discrete Fourier Transform (4.0)
* Version 4.0 (Rev. 11)
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
DisplayPort (7.0)
* Version 7.0
* Fixed YCbCr Enable parameter propagation issue through GUI
* Fixed Quad pixel mode selection issue through GUI
* Fixed the GUI selection issue for additional transceiver control and status ports
* Fixed the GTREFCLK1 grounding issue in RX targeted to UltraScale family
* Fixed 4-Lane audio issue in DisplayPort RX when TX sends minimum audio packet length of 16
* Updated EDID IIC as a standard IIC interface
* Changes to HDL library management to support Vivado IP simulation library
* Fixed extra BS symbol issue in DisplayPort TX
* Fixed RX Training Lost interrupt issue when video is coming
* Revision change in one or more subcores
DisplayPort RX Subsystem (2.0)
* Version 2.0
* Added 16-Bit GT interface support
* Added native video Interface support
* Added pixel mode support in native video mode
* Revision change in one or more subcores
DisplayPort TX Subsystem (2.0)
* Version 2.0
* Added 16-Bit GT interface support
* Added native video Interface support
* Added pixel mode support in native video mode
* Revision change in one or more subcores
Distributed Memory Generator (8.0)
* Version 8.0 (Rev. 10)
* Delivering only Verilog simulation model, Stopped delivery of vhdl simulation model.
Divider Generator (5.1)
* Version 5.1 (Rev. 10)
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
ECC (2.0)
* Version 2.0 (Rev. 11)
* Fixed warnings seen in simulations for undeclared nets
Ethernet PHY MII to Reduced MII (2.0)
* Version 2.0 (Rev. 10)
* Optional BUFFER insertion logic added in rx and tx output clock path.C_INCLUDE_BUF user parameter added for the same.
* Revision change in one or more subcores
FIFO Generator (13.1)
* Version 13.1
* Delivering only Verilog behavioral model.
* Constraint(s) for Independent Clocks Distributed RAM FIFO is changed, which may issue a CDC-1 warning that can be safely ignored.
* Output Register option is updated to offer either Embedded Register or Fabric Register or Both Embedded and Fabric Registers.
* Updated the FIFO Generator GUI to provide Embedded Register option for Built-in FIFO when ECC mode in selected.
* Programmable Full and Programmable Empty Threshold range has been reduced for UltraScale and UltraScale+ Built-in FIFO configurations. For more information on the exact threshold range change, refer the PG(057)
* Programmable Full and Programmable Empty Threshold values were reset to its default values when the previous version of the core is upgraded to the latest version. This has been corrected
* Revision change in one or more subcores
FIR Compiler (7.2)
* Version 7.2 (Rev. 6)
* Fix for error in Sysgen parameter propagation.
* Enabled DSP48 ADREG/DREG but gate CEAD/CED to address power DRC.
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
Fast Fourier Transform (9.0)
* Version 9.0 (Rev. 10)
* Revision change in one or more subcores
Fixed Interval Timer (2.0)
* Version 2.0 (Rev. 7)
* Use upper case in bus interface logical port names
Floating-point (7.1)
* Version 7.1 (Rev. 2)
* Revision change in one or more subcores
Framer (1.0)
* Version 1.0
* Initial release
* Feature support in adding Ethernet, IP and User Datagram Protocol (UDP) header to incoming RTP packets
G.709 FEC Encoder/Decoder (2.2)
* Version 2.2 (Rev. 3)
* Propagation of OTN_RATE added for IPI.
* Revision change in one or more subcores
G.975.1 EFEC I.4 Encoder/Decoder (1.0)
* Version 1.0 (Rev. 12)
* Revision change in one or more subcores
G.975.1 EFEC I.7 Encoder/Decoder (2.0)
* Version 2.0 (Rev. 12)
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
Gamma Correction (7.0)
* Version 7.0 (Rev. 9)
* Revision change in one or more subcores
Gmii to Rgmii (4.0)
* Version 4.0 (Rev. 3)
* Updates to delay for Zynq+ devices
* Changes to HDL library management to support Vivado IP simulation library
HDCP (1.0)
* Version 1.0 (Rev. 1)
* Changes to HDL library management to support Vivado IP simulation library
* Fixed CR 894190 - Issue related to Abort and Re-read
* Fixed CR 909492 - Issue related to XOR in progress status for 2 lanes.
HDCP 2.2 Cipher (1.0)
* Version 1.0
* Initial release
HDCP 2.2 Montgomery Modular Multiplier (1.0)
* Version 1.0
* Initial release
HDCP 2.2 Random Number Generator (1.0)
* Version 1.0
* Initial release
HDCP 2.2 Receiver (1.0)
* Version 1.0
* Initial release
* Support for HDMI protocol
* Support for receiver mode
* No support for repeater or converter mode upstream interface
HDCP 2.2 Transmitter (1.0)
* Version 1.0
* Initial release
* Support for HDMI protocol
* Support for transmitter mode
* No support for repeater or converter mode downstream interface
HDMI 1.4/2.0 Receiver (1.1)
* Version 1.1
* Added reset synchronizer logic
HDMI 1.4/2.0 Receiver Subsystem (2.0)
* Version 2.0
* Added Native video interface to increase user flexibility and optimize resource
* Added support for HDCP 1.4 and 2.2
* Added 3D video support
* Updated the GUI display to have "Number of pixels per clock on Video Interface"
* Fixed issue with Link Clock failing to run at 297MHz with Hardware Evaluation License
* Changed the license type in IP Catalog to be "Purchase" which was incorrectly marked as "Included"
* Added XC7Z015clg485 device support
* Fixed issue with receiving 720p59 and 720p60 in RGB or YCbCr 444 10 bit mode
* Revision change in one or more subcores
HDMI 1.4/2.0 Transmitter (1.1)
* Version 1.1
* Added reset synchronizer logic
HDMI 1.4/2.0 Transmitter Subsystem (2.0)
* Version 2.0
* Added Native video interface to increase user flexibility and optimize resource
* Added support for HDCP 1.4 and 2.2
* Added 3D video support
* Fixed audio channel swap for some audio formats
* Fixed issue with Audio Info Frames not being sent in pass-through mode
* Fixed issue with Link Clock failing to run at 297MHz with Hardware Evaluation License
* Changed the license type in IP Catalog to be "Purchase" which was incorrectly marked as "Included"
* Added XC7Z015clg485 device support
* Updated the GUI display to have "Number of pixels per clock on Video Interface"
* Revision change in one or more subcores
High Speed SelectIO Wizard (3.0)
* Version 3.0
* Async/None/Fractional Mode for Rx External Clock to Data alignment is marked Beta. These types of applications require specialized extra logic designs to handle data recovery. For more information see AR 64216
* The Bidirectional signaling feature is available to the user as Beta, however there may be modification required depending on the application. Please see AR 64216 for additional details.
* Enhanced example design to support mix of pin directions (Tx, Rx and Mix of Tx, Rx)
* Re-ordered the bytegroups in Pin Selection tab in accordance with UG 571
* Default configuration changed to "Edge DDR" for Rx External Clock to Data
* Changes to HDL library management to support Vivado IP simulation library
* Ability to select PLL output clock as RIU clock.
* User selectable placement of PLL logic in core or example design to enable sharing of PLL between multiple interfaces
* Removed PLL CLKFBOUT port selection
* Enhanced Rx Alignment through FIFO_RD_EN control logic.
* Valid Range of TX Delay Value is modified to 1 - 1250 ps from 0 - 1250 ps
* Added user configurable Bitslip Training Pattern
* Logic to drive Bitslip port added in IP wrapper. New ports added- start_bitslip, rx_bitslip_sync_done, rxtx_bitslip_sync_done
* Attribute Updates, mainly for Tx Data Alignment
* Configurable power-on value of Tx Bitslice serial output
* Advanced Strobe configuration to enable designs with data strobed using two complementary strobes
* Configurable Differential and Single Ended IO Standards and their properties - Pre-Emphasis, Equalization and Termination
* Provided user choice to append pin numbers to the configurable signal names
* Enhanced the data speed support up to 1600 Mbps for serialization factor 4, for applicable devices
* Ability to configure any number of pins as Clock Forward pin
IBERT 7 Series GTH (3.0)
* Version 3.0 (Rev. 12)
* Removed redundant rxclkoutfabric and txclkoutfabric pins
* Revision change in one or more subcores
IBERT 7 Series GTP (3.0)
* Version 3.0 (Rev. 11)
* Removed redundant rxclkoutfabric and txoutclkfabric pins
* Revision change in one or more subcores
IBERT 7 Series GTX (3.0)
* Version 3.0 (Rev. 12)
* Removed redundant rxoutclkfabric and txoutclkfabric pins
* Added a new BUFG instance for the input of MMCM clock input for system clock divider
* Revision change in one or more subcores
IBERT 7 Series GTZ (3.1)
* Version 3.1 (Rev. 9)
* Fixed the linerate value mismatch in Serial IO Analyzer
IBERT UltraScale GTH (1.3)
* Version 1.3 (Rev. 2)
* Added support for Kintex UltraScale monolithic parts.
* Revision change in one or more subcores
IBERT UltraScale GTY (1.2)
* Version 1.2 (Rev. 2)
* Added support for Virtex UltraScale Plus devices (GTY)
* Added support for 36 quads.
* Revision change in one or more subcores
IEEE 802.3 25G RS-FEC (1.0)
* Version 1.0
* Initial release
IEEE 802.3 50G RS-FEC (1.0)
* Version 1.0
* Initial release
IEEE 802.3bj RS-FEC (1.0)
* Version 1.0 (Rev. 4)
* Non functional change to improve simulation time.
* Revision change in one or more subcores
ILA (Integrated Logic Analyzer) (6.1)
* Version 6.1
* Updated the IP to support 2 Windows & 1 Sample count configuration
* Number of comparator increased from 1 to 16 in basic mode and 4 to 16 in advanced mode
* Updated probe data width register
* Revision change in one or more subcores
IOModule (3.0)
* Version 3.0 (Rev. 4)
* Added support for extended address
* Allow selection of single interrupt output bus interface
* Added parameter enablement expressions for user parameters
Image Enhancement (8.0)
* Version 8.0 (Rev. 9)
* Changed Virtex UltraScale family status to production.
* Revision change in one or more subcores
Interlaken (1.9)
* Version 1.9
* Retransmission enabled in GUI
* Both QPLL0 and QPLL1 support for GT DRP
* Added ability to change initial clock frequency
* Improved shared logic option
* Support for the clocking and reset logic wrappers outside the core when shared logic is in example design
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
Interleaver/De-interleaver (8.0)
* Version 8.0 (Rev. 9)
* Revision change in one or more subcores
JESD204 (7.0)
* Version 7.0
* Revised architecture to reduce latency through the receive core
* Added rx_start_of_multiframe and rx_end_of_multiframe ports to the receive core
* Removed tx_aclk and rx_aclk output ports
* Optimized TX and RX to improve timing
* Added BUFGs on drpclk and axiclk in example design. 7-Series only
* Reduced maximum number of lanes from 12 to 8
* Removed LMFC Buffer selection from GUI
* Functionality of register 0x3C (Link Error Status for lanes 8 to 11) has changed, now returns debug information. See PG066 for more information
* Differential global clock input has been removed and replaced with single ended tx/rx_core_clk input. UltraScale configurations only. See PG066 for information on how to drive new clock input
* Global Clock option has been removed from GUI for UltraScale configurations only
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
JESD204 PHY (3.1)
* Version 3.1
* Fixed issue where transceiver settings were incorrectly set if the channel did not start from a QUAD boundary and had more than 4 lanes. UltraScale only (AR66029)
* Added 64-bit data path with 64b/66b encoding/decoding. UltraScale only
* Added GUI option to select transceiver channel attenuation. UltraScale only
* Removed ports gt_rxdfelpmreset and gt_rxlpmen from Transceiver Debug bus when AXI4-Lite is enabled, ports are now controlled using a register in this case. See PG198 for more information
* Fixed issue where powering down a lane would cause rx reset done not to go high
* Fixed issue where powering down the first channel would cause rxoutclk to have the wrong frequency
* A BUFG_GT has been added to the tx/rxoutclk output when support logic is included in the core. UltraScale configurations only
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
JTAG to AXI Master (1.1)
* Version 1.1 (Rev. 2)
* Updated FIFO generator from v13.0 to v13.1
* Revision change in one or more subcores
LMB BRAM Controller (4.0)
* Version 4.0 (Rev. 8)
* Added support for extended address
* Support for Virtex UltraScale devices at Production status
LTE DL Channel Encoder (3.0)
* Version 3.0 (Rev. 10)
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
LTE Fast Fourier Transform (2.0)
* Version 2.0 (Rev. 11)
* Revision change in one or more subcores
LTE PUCCH Receiver (2.0)
* Version 2.0 (Rev. 10)
* Revision change in one or more subcores
LTE RACH Detector (2.0)
* Version 2.0 (Rev. 10)
* Corrected CE signal name case in IP-XACT port description
* Revision change in one or more subcores
LTE UL Channel Decoder (4.0)
* Version 4.0 (Rev. 10)
* Fix in common c model utilities package for handling of arrays of real types in Matlab
* Revision change in one or more subcores
Local Memory Bus (LMB) 1.0 (3.0)
* Version 3.0 (Rev. 8)
* Added support for extended address
MIPI CSI-2 Rx Controller (1.0)
* Version 1.0 (Rev. 2)
* Core XDC updated as per subcore changes
* FIFO version update from 13.0 to 13.1
MIPI CSI-2 Rx Subsystem (2.0)
* Version 2.0
* XPM_CDC integration
* DPHY v2.0 integration
* Added GUI option to include or exclude(Beta feature) Video Format Bridge(VFB).
* Support for additional data types in VFB(User defined byte based data types)
* Added GUI option to include or exclude shareable logic resources in the core(MMCM and PLL)
* Clocking architecture updates in MIPI D-PHY RX High-Speed datapath
* High-Speed SelectIO IP integration
* Enhanced IO planner feature with more I/O selection options
* IP top level ports will differ compared to mipi_csi2_rx_subsystem_1_0 IP due to Shared Logic feature
* Revision change in one or more subcores
MIPI D-PHY (2.0)
* Version 2.0
* Added GUI option to include or exclude shareable logic resources in the core
* Resource optimizations
* Latency improvements on MIPI D-PHY RX IP configurations
* Clocking architecture updates in MIPI D-PHY RX High-Speed datapath
* High-Speed SelectIO IP integration
* Enhanced I/O planner feature with more I/O selection options
* rxvalidhs generation is updated such that it will not go Low in the middle of the HS data transfer
* Added GUI option to include or exclude HS and ESC TIMEOUT counters/registers
* enable signal from PPI is decoupled from lane initialization and de-assertion of enable will not affect lane initialization status
* IP top level ports will differ compare to mipi_dphy_1_0 IP due to Shared Logic feature
MIPI DSI Tx Controller (1.0)
* Version 1.0
* Initial release
MIPI DSI Tx Subsystem (1.0)
* Version 1.0
* Initial release
* Subsystem with integrated DPHY and DSI Tx Controller.
* Support for 1 to 4 DPHY lanes
* AXI4-Stream Video Input interface
Mailbox (2.1)
* Version 2.1 (Rev. 5)
* No changes
Memory Helper Core (1.2)
* Version 1.2
* Support for Vivado 2016.1
Memory Interface Generator (MIG 7 Series) (3.0)
* Version 3.0
* Support for RLDRAM II, QDRII+ SRAM and RLDRAM 3 designs on Zynq Kintex-7 Architectured devices.
MicroBlaze (9.6)
* Version 9.6
* Added support for extended address
* Improved sleep functionality
* Enhanced support for AXI-4 access permissions
* Support for Virtex UltraScale devices at Production status
MicroBlaze Debug Module (MDM) (3.2)
* Version 3.2 (Rev. 5)
* Avoid upgrade warnings
* Added parameter enablement expressions for user parameters
MicroBlaze MCS (3.0)
* Version 3.0
* Repackaged as a hierarchical IP, no functional changes
* Export hardware to SDK using Vivado instead of IP specific export. Due to this change software may need to be updated to modify IP parameter names.
* Added option to enable Error Correction Codes (ECC) on the internal Block RAM
* Added option to set MicroBlaze optimization (area or performance)
* Support for Virtex UltraScale devices at Production status
* Added parameter enablement expressions for user parameters
* Revision change in one or more subcores
Multiplier (12.0)
* Version 12.0 (Rev. 11)
* Updated DSP48 register settings for improved power characteristics as suggested by report_drc. No functional changes.
* Revision change in one or more subcores
Multiply Adder (3.0)
* Version 3.0 (Rev. 9)
* Revision change in one or more subcores
Mutex (2.1)
* Version 2.1 (Rev. 6)
* Added parameter enablement expressions for user parameters
PCIE PHY IP (1.0)
* Version 1.0
* Initial release
Partial Reconfiguration Controller (1.0)
* Version 1.0 (Rev. 3)
* Changed the default GUI tab to the core's symbol.
* HASH(0x1230dde0)
* HASH(0x1230ddf0)
* HASH(0x1230de10)
* The behavior of rm_reset has been changed in some cases after a Power on Reset. See the Product Guide for more information.
* Revision change in one or more subcores
Partial Reconfiguration Decoupler (1.0)
* Version 1.0 (Rev. 2)
* Made the core production level
* Fixed a bug where the AXI4-Stream TSTRB and TKEEP signal widths were not being set correctly in IPI
* Fixed a bug where the AXI4-MM WSTRB signal width was not being set correctly in IPI
* Fixed a bug where the AXI4-MM fixed width signals were getting converted to 1 bit wide in IPI
* Updated the IPI propagation code to handle cases where the direction of a signal in an interface has to be changed during propagation
* Changes to HDL library management to support Vivado IP simulation library
Peak Cancellation Crest Factor Reduction (6.0)
* Version 6.0 (Rev. 4)
* Fix for CCDF flaring seen in some cases for WCFR standalone mode
* Improved QoR for UltraScale devices
* Revision change in one or more subcores
Processor System Reset (5.0)
* Version 5.0 (Rev. 9)
* Updated bd.tcl post config procedure. No functional change.
QDRII+ SRAM (MIG) (1.2)
* Version 1.2
* Support for Vivado 2016.1
* A Bitslice reset was added 20us after BISC has completed.
* Revision change in one or more subcores
QDRIV SRAM (MIG) (1.1)
* Version 1.1
* Initial QDRIV public release.
QDRIV SRAM PHY IP (1.1)
* Version 1.1 (Rev. 1)
* Support for Vivado 2016.1
QSGMII (3.3)
* Version 3.3 (Rev. 4)
* Changed version of helper core gig_ethernet_pcs_pma from v15_1 to v15_2
* Changes to HDL library management to support Vivado IP simulation library
* Support to run Rx path on recovered clock
* Revision change in one or more subcores
RAM-based Shift Register (12.0)
* Version 12.0 (Rev. 9)
* Fixed GUI COE file handling
* Revision change in one or more subcores
RGB to YCrCb Color-Space Converter (7.1)
* Version 7.1 (Rev. 7)
* Revision change in one or more subcores
RLDRAM3 (MIG) (1.2)
* Version 1.2
* Updated for 2016.1
* Added support for RLDRAM3 1200 MHz part.
* Resolved issues related to using custom CSV. See Xilinx Answer 66678 for details.
* Resolved hardware failure at low frequency range. See Xilinx Answer 65371 for details.
* Revision change in one or more subcores
RXAUI (4.3)
* Version 4.3 (Rev. 4)
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
Reed-Solomon Decoder (9.0)
* Version 9.0 (Rev. 11)
* Revision change in one or more subcores
Reed-Solomon Encoder (9.0)
* Version 9.0 (Rev. 10)
* Revision change in one or more subcores
S/PDIF (2.0)
* Version 2.0 (Rev. 11)
* Helper core version fifo_generator_v13_1 update and safety circuit enablement for safe fifo reset operation. No other functional changes.
SC EXIT (1.0)
* Version 1.0
* Initial release
SC MMU (1.0)
* Version 1.0
* Initial release
SC SI_CONVERTER (1.0)
* Version 1.0
* Initial release
SC SPLITTER (1.0)
* Version 1.0
* Initial release
SC TRANSACTION_REGULATOR (1.0)
* Version 1.0
* Initial release
SMPTE 2022-1/2 Video over IP Receiver (2.0)
* Version 2.0 (Rev. 5)
* Added Production support for Virtex UltraScale
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
SMPTE 2022-1/2 Video over IP Transmitter (2.0)
* Version 2.0 (Rev. 5)
* Added Production support for Virtex UltraScale
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
SMPTE SD/HD/3G-SDI (3.0)
* Version 3.0 (Rev. 7)
* Added support for Kintex UltraScale and Virtex UltraScale
SMPTE ST 2059 (1.0)
* Version 1.0
* Initial release
* ST2059 Source
* One PPS Output
* Generates Video and/or Audio alignment (synchronization) signals in accordance with SMPTE ST2059-1 standard.
* Incorporates very high precision IEEE1588 RTC timer
* Supports generation of Time Code (hours, minutes, seconds and frame number)
* Supports drop frame time code
* Includes PTP Master-locked reference clock generators, for external video and/or audio PLL
* Control of the core and reading status information can be done via a AXI-lite interfaces
SMPTE UHD-SDI (1.0)
* Version 1.0 (Rev. 2)
* Added support for Virtex UltraScale
SMPTE2022-5/6 Video over IP Receiver (5.0)
* Version 5.0 (Rev. 4)
* Virtex UltraScale production support
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
SMPTE2022-5/6 Video over IP Transmitter (4.0)
* Version 4.0 (Rev. 6)
* Updated the core constraint XDC file
* Virtex UltraScale production support
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
SPI-4.2 (13.0)
* Version 13.0 (Rev. 8)
* Repackaged demo testbench pl4_testcase_pkg.v file
ST2022-56 De-Packetizer (1.0)
* Version 1.0
* Initial release
* Feature support in converting received SMPTE2022-6 RTP packets into SDI video stream (transmitted over SDI over AXIS)
ST2022-56 Packetizer (1.0)
* Version 1.0
* Initial release
* Feature support in converting SDI video stream (transmitted over SDI over AXIS) into a media datagram stream in accordance with the SMPTE2022-6 protocol
SelectIO Interface Wizard (5.1)
* Version 5.1 (Rev. 7)
* Added option in GUI (Forward divide clock) to forward divided clock or serial clock
Serial RapidIO Gen2 (4.0)
* Version 4.0 (Rev. 3)
* added optional transceiver ports
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
SmartConnect AXI2SC Bridge (1.0)
* Version 1.0
* Initial Release
SmartConnect Node (1.0)
* Version 1.0
* Initial release
SmartConnect SC2AXI Bridge (1.0)
* Version 1.0
* Initial release
SmartConnect Switchboard (1.0)
* Version 1.0
* Initial release
Soft Error Mitigation (4.1)
* Version 4.1 (Rev. 5)
* No changes
System Cache (3.1)
* Version 3.1 (Rev. 3)
* Avoid upgrade warnings
* Corrected tooltip
* Support for Virtex UltraScale devices at Production status
* Added parameter enablement expressions for user parameters
System Management Wizard (1.3)
* Version 1.3
* SYSMON slaves are made disabled by default.
Timer Sync 1588 (1.2)
* Version 1.2 (Rev. 3)
* No changes
Tri Mode Ethernet MAC (9.0)
* Version 9.0 (Rev. 4)
* Added new feature for Internal mode - Ability to use PHY RXOUTCLK clock for RX datapath
* Fixed bug in 1G Example Design Pattern Generator module, VHDL version, in which the output frames were of incorrect size
* Fixed Statistics Bug - Simulation Fatal Error when accessing registers which have been disabled by core customization
* Fixed corner case Statistics bug - RX Undersize Frames counter and RX Fragment Frames counter not incrementing correctly in absence of preamble bytes
* Fixed corner case bug in transmit logic - MAC may loose couple of input frame bytes in cases where user initiates a back-to-back frame transfer and asserts error at very early stages of frame transmission
* Fixed corner case bug in 2.5G transmit logic - MAC may not corrupt the TX frame if the user error indication is received at very early or very late stages of frame transmission
* Corrected RX Clock name in the User PHY Timing XDC file for RGMII mode
* For UltraScale devices in RGMII - Added DONT_TOUCH attribute for the parallel clock buffers on RX Clock to prevent them from being optimized
* Updates to Example Design XDC - Updated PIN LOCs for device XCKU040 for GMII and RGMII modes; Provided reference PIN LOCs for these UltraScale+ devices: XCKU9P, XCVU3P and XCZU3EG for GMII mode
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
UltraScale 100G Ethernet Subsystem (1.9)
* Version 1.9
* Changed top level signal names which contains *_vl_* with *_pcsl_*
* Both QPLL0 and QPLL1 clock support for GT DRP
* 322.161MHz clock support for runtime switchable case
* Added shared logic selection for CAUI4
* Support for the clocking and reset logic wrappers outside the core when shared logic is in example design
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
UltraScale FPGA Gen3 Integrated Block for PCI Express (4.2)
* Version 4.2
* Modified the width of pipe_tx_*_sigs, common_commands_in and common_commands_out
* Added the startup_fcsbts signal to the IPI startup interface
* Added constant value for TXRATE and RXRATE pins based on link speed selection in the IP constraint to avoid synthesis and implementation warnings
* Added support for 'ASPM Option - L1 Supported' and removed 'L0s_L1_Entry Supported' option (Xilinx Answer - 66347)
* Modified the mapping of logical and physical external pipe interface ports for End Point configurations so that it can be connected to Root Port instance directly
* Added two new ports to transceiver debug interface section: gt_dmonfiforeset gt_dmonitorclk
* Fixed issue with the default values of 'Base Class Menu' and 'Sub Class Interface Menu' and the update of 'Class Code' parameter when 'Lookup Assistant' option is used
* Added support for defense grade Kintex UltraScale devices - xqku040-rfa1156,xqku040-rba676,xqku060-rfa1156 and xqku095-rfa1156
* Added clock name for all clocks generated by the IP
* Fixed falling edge receiver detect DRP logic
* Revision change in one or more subcores
UltraScale FPGAs Transceivers Wizard (1.6)
* Version 1.6 (Rev. 2)
* Improved performance and functionality of UltraScale+ GTH and GTY serial transceivers via parameter updates
* Added new transceiver configuration preset options
* Changed the lifecycle status of several UltraScale transceiver configuration presets to Production
* Replaced type of synchronizer in buffer bypass helper blocks to tolerate absence of clock during reset assertion
* Adjusted the programmable termination voltage options for UltraScale+ GTY serial transceivers
* Increased Kintex UltraScale GTH maximum line rate for -1LV speed grade devices from 10.3125 Gb/s to 12.5 Gb/s
* Adjusted line rate and associated frequency limits for GTY transceivers in -1HV speed grade devices to match Virtex UltraScale FPGAs Data Sheet
* Adjusted minimum CPLL VCO frequency for UltraScale+ GTH and GTY transceivers according to silicon errata
* Fixed a bug in the customization GUI that prevented selection of a legal user data width when targeting maximum line rate for some devices
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
UltraScale Soft Error Mitigation (3.1)
* Version 3.1
* Production release of UltraScale IP
* Add support for Detect modes
* Pre-production release of UltraScale+ IP, supports ku9p devices
* Verified IP is compatible with authentication and encrypted (AES) bitstream flows
* Classification feature support for VU440 device
* Changes to HDL library management to support Vivado IP simulation library
* Add example logic to demonstrate how to monitor IP status signals and heartbeat
* Address erroneous correction of single-bit ROM errors
* Modify the behavior of status signals to assert(fatal error condition) when a double-bit(uncorrectable) ROM error occurs
UltraScale+ 100G Ethernet Subsystem (1.0)
* Version 1.0
* Initial release
* Changes to HDL library management to support Vivado IP simulation library
UltraScale+ PCI Express Integrated Block (1.1)
* Version 1.1
* Modified Customization GUI View for PF BARs,SRIOV BARs,PCIe ID and ClassCode parameters
* Support is enabled for all UltraScale+ parts and packages that support PCIe.
* Added gtwizard subcore (HIP) support, which includes GTHE4 and GTYE4.
* Added support for All link widths/speeds (Gen1/2/3 to x1,x2,x4,x8,x16)
* Added support for Root Port(RP) Mode and RP Example Design synthesis/simulation for all available configurations.
* Revision change in one or more subcores
VIO (Virtual Input/Output) (3.0)
* Version 3.0 (Rev. 11)
* IP generation error for 256 probe_outs fixed
* Revision change in one or more subcores
Video AXI4S Remapper (1.0)
* Version 1.0
* First version released
* Supported devices and production status are determined automatically, to simplify support for future devices
* Changes to HDL library management to support Vivado IP simulation library
Video Deinterlacer (4.0)
* Version 4.0 (Rev. 10)
* Changes to HDL library management to support Vivado IP simulation library
Video In to AXI4-Stream (4.0)
* Version 4.0 (Rev. 2)
* Supported devices and production status are now determined automatically, to simplify support for future devices
* Revision change in one or more subcores
Video Mixer (1.0)
* Version 1.0
* First version released
Video On Screen Display (6.0)
* Version 6.0 (Rev. 10)
* Revision change in one or more subcores
Video PHY Controller (2.0)
* Version 2.0 (Rev. 1)
* HDMI protocol support added for GTPE2 and GTHE4
* DisplayPort protocol support for GTPE2
* Enable generation unencrypted video PHY controller related source code files
* Fixed generation failure due to configuration with HDMI protocol selected on either TX or RX side only
* Removed example design support for this IP as reference design is available for DP and HDMI that showcase PHY
* Removed unnecessary warnings and debug messages display during core generation
* Enable support for HDMI TX only protocol or RX only protocol configuration
* Revision change in one or more subcores
Video Processing Subsystem (2.0)
* Version 2.0
* Added additional Video Processing configurability (Deinterlacing Only, Color Space Conversion Only, Chroma Resampling Only)
* Added additional configurability to the Full Fledged Video Processing functionality
* Changed default Video Processing functionality to Full Fledged
* Changed example design video clock from 300 MHz to 200 MHz
* Supported devices and production status are now determined automatically, to simplify support for future devices
* The Video Processing Subsystem is susceptible to Windows path length restrictions. See (Xilinx Answer 66692) for details.
* Revision change in one or more subcores
Video Scaler (8.1)
* Version 8.1 (Rev. 8)
* Revision change in one or more subcores
Video Test Pattern Generator (7.0)
* Version 7.0 (Rev. 2)
* Supported devices and production status are now determined automatically, to simplify support for future devices
* Improved support for multiple instances
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
Video Timing Controller (6.1)
* Version 6.1 (Rev. 7)
* Supported devices and production status are now determined automatically, to simplify support for future devices
* Fixed clock enable to produce correct video timing
Video over IP FEC Receiver (2.0)
* Version 2.0
* Upgrade FEC RX core to support ST2022-5/6 packets
* Update GUI bus interface naming to match the HDL interface ports
* Redundant DDR wr protection, correct dup and corrected counter fix
* fix for corruption in packet due AXI-MM arbiter reject packet to mem_wr_ctrl
* bug fix in fec_processing_delay for big L/D fec meta fifo full bug
* Revision change in one or more subcores
Video over IP FEC Transmitter (2.0)
* Version 2.0
* Upgrade FEC TX core to support ST2022-5/6 standard
* RTL port naming change and update GUI bus interface naming to match the HDL interface ports
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.2)
* Version 4.2
* Modified the width of pipe_tx_*_sigs, common_commands_in and common_commands_out
* Modified the mapping of logical and physical external pipe interface ports for EP configurations so that it can be connected to Root Port instance directly
* Added support for 'ASPM Option-L1 Supported' and removed 'L0s_L1_Entry_Supported option'
* Added mmcm_lock port which corresponds to all clocks generated by the IP
* Fix asynchronous clocking mode for Gen1/2 and removed the extra BUFG
* Added name for all clocks generated by the IP in the constraint file
* Fixed issue with the default values of 'Base Class Menu' and 'Sub Class Interface Menu' and the update of 'Class Code' parameter when Lookup Assistant option is used
* Removed the dependency of 'Include Shared Logic(clocking)in example design' on 'External PIPE Interface pipe mode simulation option'. No changes made to the 'Enable Pipe mode Simulation' option
* Revision change in one or more subcores
Viterbi Decoder (9.1)
* Version 9.1 (Rev. 6)
* Revision change in one or more subcores
XADC Wizard (3.3)
* Version 3.3
* Added DDR3 voltage levels for VCCDDRO Alarm.
* Enabled ADC Offset and Gain Calibration and the Sensor Offset and Gain Calibration enabled by default.
XAUI (12.2)
* Version 12.2 (Rev. 4)
* Changes to HDL library management to support Vivado IP simulation library
* Revision change in one or more subcores
YCrCb to RGB Color-Space Converter (7.1)
* Version 7.1 (Rev. 7)
* Revision change in one or more subcores
ZYNQ UltraScale+ MPSoC (1.1)
* Version 1.1
* Availability of up to 4 PL reset signals using GPIO through EMIO
* Availability of default PL clock signal.
* FIFO & PTP interfaces on GEM are always available through EMIO
* dp_aux_data_oe_n is enabled when Display Port is enabled along with DPAUX through EMIO
* Update in PSS_IO attributes, All Io attribute parameters including those of DDR are being dumped in HDL.(*PSS_IO= Signal Name, DiffPair Type, DiffPair Signal,Direction, Site Type, IO Standard, Drive (mA), Slew Rate, Pull Type, IBIS Model, ODT, OUTPUT_IMPEDANCE) and its corresponding signals are being written into HDL
* Changes in PSS_Power, Clock frequency, data width of DDR3, VCO updated.
* F2P Interrupt logic updated
* Debug clocks added
* EMIO, O, I, and T wire added to reflect the same number of EMIO (Outputs).
ZYNQ7 Processing System (5.5)
* Version 5.5 (Rev. 3)
* No changes
ZYNQ7 Processing System BFM (2.0)
* Version 2.0 (Rev. 5)
* No changes
axi_sg (4.1)
* Version 4.1 (Rev. 2)
* No changes
interrupt_controller (3.1)
* Version 3.1 (Rev. 3)
* No changes
lib_bmg (1.0)
* Version 1.0 (Rev. 4)
* Revision change in one or more subcores
lib_cdc (1.0)
* Version 1.0 (Rev. 2)
* No changes
lib_fifo (1.0)
* Version 1.0 (Rev. 4)
* No changes
lib_pkg (1.0)
* Version 1.0 (Rev. 2)
* No changes
lib_srl_fifo (1.0)
* Version 1.0 (Rev. 2)
* No changes
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 54480 | LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools | N/A | N/A |
| AR# 66930 | |
|---|---|
| 日期 | 06/08/2016 |
| 状态 | Active |
| Type | 版本说明 |
| Tools | |