AR# 67617

描述

Version Found: v1.1 Rev1 (Vivado 2016.2)

Version Resolved and other Known Issues: (Xilinx Answer 65751)

Vivado 2016.2 does not allow to generate x16Gen3 configuration for UltraScale+ PCI Express Integrated Block core with -1L and -2L devices.

This article is part of the PCI Express Solution Centre

解决方案

This is a known issue to be fixed in a future release of the core. Please install the patch provided in Vivado 2016.2 as described below:

METHOD 1:

1. Navigate to the $XILINX_VIVADO/patches directory (create this directory if it does not exist)
2. Extract the contents of the ".zip" archive to a directory starting with the name AR67617
   Note: most extraction tools will allow you to automatically create a directory with the same name as the zip file
3. Run Vivado software tools from the original install location.

METHOD 2:

1. Create a separate directory for the patched files
2. Extract the contents of the ".zip" archive to the desired patch directory location
3. Set the MYVIVADO environment variable to point to the Vivado directory under this patch directory
   For example:
   set MYVIVADO=C:\MYVIVADO\vivado-patch-AR67617\vivado\
4. Run Vivado software tools from the original install location.

Note: For -1L devices, the following performance improvement settings must be applied manually to meet timing:

set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE AltSpreadLogic_high [get_runs impl_1]
set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE NoTimingRelaxation [get_runs impl_1]
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]

Revision History:

08/06/2016 - Initial Release

附件