描述
While debugging or running an application on a Zynq-7000 or Zynq MPSoC device with the debugger attached to the target, triggering a reset causes the core to be halted at the reset vector:
xsct% connect
tcfchan#0
xsct% ta
1 PS TAP
2 PMU
3 PL
4 PSU
5 RPU (Reset)
6 Cortex-R5 #0 (RPU Reset)
7 Cortex-R5 #1 (RPU Reset)
8 APU
9 Cortex-A53 #0 (Running)
10 Cortex-A53 #1 (Power On Reset)
11 Cortex-A53 #2 (Power On Reset)
12 Cortex-A53 #3 (Power On Reset)
xsct% Info: Cortex-A53 #0 (target 9) Stopped at 0xffff0000 (Reset Catch)
xsct%
解决方案
This is expected behavior.
By default, the System Debugger enables the vector catch feature to halt the processor core at the reset vector when a core reset is triggered.
This feature can be disabled for specific cores through XSDB using the configparams command:
xsct% connect -url 172.21.166.118:3121
tcfchan#0
xsct% ta
1 PS TAP
2 PMU
3 PL
4 PSU
5 RPU (Reset)
6 Cortex-R5 #0 (RPU Reset)
7 Cortex-R5 #1 (RPU Reset)
8 APU
9 Cortex-A53 #0 (Running)
10 Cortex-A53 #1 (Power On Reset)
11 Cortex-A53 #2 (Power On Reset)
12 Cortex-A53 #3 (Power On Reset)
xsct% configparams disable-access 1
xsct% ta
1 PS TAP
2 PMU
3 PL
4 PSU
5 RPU (Access Disabled)
6 Cortex-R5 #0 (RPU Access Disabled)
7 Cortex-R5 #1 (RPU Access Disabled)
8 APU (Access Disabled)
9 Cortex-A53 #0 (APU Access Disabled)
10 Cortex-A53 #1 (APU Access Disabled)
11 Cortex-A53 #2 (APU Access Disabled)
12 Cortex-A53 #3 (APU Access Disabled)
链接问答记录
主要问答记录
| Answer Number |
问答标题 |
问题版本 |
已解决问题的版本 |
| 66297 |
SDK - 设计助手 |
N/A |
N/A |