Version Found: v1.1 Rev2 (Vivado 2016.3)
Version Resolved and other Known Issues: (Xilinx Answer 65751)
The tactical patch provided with this answer record addresses link up issue when the "system reset polarity" option in configuration GUI is set to "active high"
This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) | Xilinx Solution Center for PCI Express |
This is a known issue to be fixed in a future release of the core, please install the tactical patch attached as described below:
METHOD 1:
Note: The "Version Found" column lists the version the problem was first discovered.
The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions. This is an issues with latency of the core.
文件名 | 文件大小 | File Type |
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AR68310_Vivado_2016_3_preliminary_rev1.zip | 1 MB | ZIP |
AR# 68310 | |
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日期 | 10/04/2017 |
状态 | Active |
Type | 已知问题 |
器件 | |
Tools | |
IP |