AR# 69327

描述

The Environment Release Notes and Licensing Guide, found on Xilinx.com, contains installation instructions, system requirements, and other general information.

This Known Issues Answer Record is a supplement to the release notes documentation and contains links to information on known issues in the design tools that might be resolved in future versions.

Xilinx Forums:

Please seek technical support via the SDAccel Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

解决方案

SDAccel 2017.1 New Features:

For More details please see (UG1238)

SDAccel Development Environment Features

RTL Kernel Support 2017.1 provides significant improvement to usability and performance for importing and optimizing RTL kernels in SDAccel:

• New RTL Kernel wizard is added to provide the user with a template for importing RTL IP into SDAccel.
• Provides scripts to build the RTL kernel into .xo (Xilinx Object) avoiding error-prone creation of kernel.xml files that were required in earlier releases.
• For Vivado experts working on optimizing performance of RTL kernels, xocc has been enhanced to include Vivado script through -custom_script during xocc -- link.
• Utilization reports are automatically generated during compilation. These reports show utilization of LUTS, Registers, BRAMs, and DSPs for the platform region, as well as for each of the kernels.

The SDAccel compiler employs mathematical techniques to identify statically the access pattern of inputs and outputs to perform better memory coalescing and burst inference. 

This is an early access feature and can be enabled with both of the following xocc options:

• --xp param:compiler.version=39
• --xp param:compiler.advancedLoopOptimizations=true

SDAccel/HLS should be able to infer a shift register pattern automatically for OpenCL kernel.

OpenCL Shifter Design Pattern is inferred if:

• The shift logic is described simply using for-loop.
• The array is initiated with 0, with assignment to the beginning or to the end for new value.
• The access points should be constant offset.

The compiler automatically decides if a shift-register is implemented in SRL or BRAM to improve better resource use and improve timing closure.

Dataflow support for OpenCL is now a production feature.

The compiler can support dataflow on functions with arbitrary sized parameters, sub functions, or loops. Dataflow can also apply to loop statements.

The xocc command to define OpenCL Compiler dataflow FIFO size is:

• --xp param:compiler.xclDataflowFifoDepth = 4

The following warning message might appear during compile:

• kernel.cl:28:17: warning: unknown attribute 'xcl_dataflow'
• ignored __attribute__ ((xcl_dataflow))
• Ignore the warning or use -k kernel_name to avoid the warning.

SDAccel introduces the OpenCL 2.0 image data type, which provides the ability to read and write to images in kernels through OpenCL 2.0 image built-ins.

The supported APIs are:

• clCreateImage() for the image types listed above.
• clGetSupportedImageFormats()
• clEnqueueReadImage()
• clEnqueueWriteImage()
• clGetImageInfo()

Enhancements to OpenCL math built-in functions to improve performance and reduce resources.

To provide better control to expert users, xocc allows users to write out the default script as well as to apply custom scripts.

• xocc -c -export_script
• xocc -c -custom_script

Changes to SDAccel platform include the following:

• XDMA enhanced to support two Physical Functions to provide one PF for secure management.
• AXI Firewall at XDMA Full AXI4 and two AXI Lite interfaces to insulate the platform from hangs caused by AXI protocol violations in kernels.
• Feature ROM to embed platform data in a ROM in the DSA to enable Run Time checks.
• Bitstream download through ICAP on all platforms rather than MCAP for faster downloads.

Introducing support for Kintex UltraScale FPGA KCU1500 Reconfigurable Acceleration PCIe card.