When using the JESD204 PHY (v3.1) or later, if you are not using the AXI-Lite interface or Transceiver Debug, RXLPMEN is set to 1 for lane 1 only and set to 0 for all other lanes.
To work around this issue, either
1) Enable the AXI-Lite interface which will correct the problem.
Or
2) Enable the "Additional transceiver control and status ports" in the JESD204 PHY core GUI to expose the additional transceiver ports. Then drive all of the "gt_rxlpmen" input bits to 1 from outside the core.
This issue will be resolved in the Vivado 2017.3 version of the JESD204 PHY (v4.0).
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 61911 | LogiCORE IP JESD204 PHY core - Release Notes and Known Issues | N/A | N/A |
| AR# 69508 | |
|---|---|
| 日期 | 07/26/2017 |
| 状态 | Active |
| Type | 综合文章 |
| IP | |