2. 技术支持
  3. AR# 6996:
  4. AR# 69960: Zynq UltraScale+ MPSoC, Zynq-7000, Vivado 2017.3 - Upgrading to 2017.3 without validating can corrupt the Processing System Block

AR# 69960

|

Zynq UltraScale+ MPSoC, Zynq-7000, Vivado 2017.3 - Upgrading to 2017.3 without validating can corrupt the Processing System Block

描述

If a design with a Zynq-7000 or Zynq UltraScale+ block is modified but not validated before upgrading in Vivado 2017.3, the IP block can become corrupted, resulting in incorrect operation.

解决方案

To work around this issue, be sure to validate the design before opening/upgrading the design in Vivado 2017.3.

If the design is upgraded to Vivado 2017.3 without validation, the PS block can instead be replaced - this can be accomplished by parameterizing a new PS block and then using the replace_bd_cell old_instname new_instname Tcl command to swap the IP instances without having to reconnect interfaces.

For designs unable to be validated, a patch is attached, which can be used in Vivado 2017.3 and Vivado 2017.3.1.

This issue will be fixed starting in Vivado 2017.4.

附件

文件名 文件大小 File Type
AR69960_vivado_2017_3_preliminary_rev1.zip 21 MB ZIP

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
70040 Zynq UltraScale+ MPSoC - WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter PSU__M_AXI_GP2__FREQMHZ() on '/zynq_ultra_ps_e_0' with propagated value(). Command ignored N/A N/A
AR# 69960
日期 10/25/2017
状态 Active
Type 综合文章
器件
Tools
IP
People Also Viewed