After upgrading a design to Vivado 2017.3, when changing the clock frequency of a PS AXI interface, the following warning can occur.
How do I resolve it?
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter PSU__M_AXI_GP2__FREQMHZ() on '/zynq_ultra_ps_e_0' with propagated value(). Command ignored
To work around this issue after an upgrade to Vivado 2017.3, the PS block can be replaced.
This can be accomplished by parameterizing a new PS block and then using the following Tcl command to swap the IP instances without having to reconnect interfaces:
replace_bd_cell old_instname new_instname
Alternatively, to avoid this issue you can apply the patch in (Xilinx Answer 69960) to Vivado 2017.3 before upgrading a previous design.
This upgrade issue will be fixed starting in Vivado 2017.4.
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
69960 | Zynq UltraScale+ MPSoC, Zynq-7000, Vivado 2017.3 - Upgrading to 2017.3 without validating can corrupt the Processing System Block | N/A | N/A |
AR# 70040 | |
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日期 | 11/02/2017 |
状态 | Active |
Type | 综合文章 |
器件 | |
Tools | |
IP |