AR# 70324

描述

Version Found: v4.0/v4.0 (Rev1)

Version Resolved and other Known Issues: (Xilinx Answer 65443)

• For H2C transfer, two Read Requests are created and two completions returned but the second completion does not appear on the AXI bus.
• For C2H transfer, s_axis_cc_tready is deasserted.

Issue 2:

• H2C transfer hangs when the AXI data width is 128-bit and 64 bit addressing mode is enabled.
  

This article is part of the PCI Express Solution Centre

解决方案

For instruction on installing the patch, please check the instructions in the 'patch_readme' directory in the attached patch file.

Two separate patches for Vivado 2017.3 and 2017.4 are provided in this answer record. Please use the corresponding patch for the Vivado version you are using.

Note: "Version Found" refers to the version where the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

02/05/2018 - Initial Release

附件