AR# 70450

描述

I have an SDx/SDAccel Design where the implementation flow does not meet timing.

It appears that the Frequency downscaling is not being applied, and the compiler is suggesting that the frequency be reduced using a switch.

The messaging is as follows:

What are the conditions under which downscaling is possible?

解决方案

There are several clock domains which exist within the reconfigurable region of a DSA.

When kernels are linked in and the reconfigurable region is re-implemented as part of the XOCC flow, timing closure is attempted for all timing paths.

However, only the kernel clock domains (which are the clock domains which are used for all synchronous paths to, from, and within kernels) can be scaled down in the event that their paths contain setup violations after this re-implementation. 

Other clock domains in the reconfigurable region, such as those for the MIG memory controllers, cannot be scaled down; so if they fail to close timing, you will get the error described above.

The error message advises to reduce the kernel clock frequency target because in most cases like this, timing paths on the kernel clock domain contain some large setup violations (i.e. large WNS). 

This by itself is okay because the kernel clock domain is scalable. 

However, those large violations can also indirectly cause other marginal paths on non-scalable clock domains to fail setup requirements, because of the way in which Vivado tools prioritize timing closure. 

Reducing the kernel clock target often also reduces the amount of effort the tools need to put into closing the important non-scalable clock paths.