Version Found: v4.1
Version Resolved and other Known Issues: (Xilinx Answer 65443)
When DMA Subsystem for PCI Express IP is configured in Bridge mode, performance degradation is observed in Gen3x8 256 bit configuration.
The performance degradation occurs because the completion packet for the Slave AXI Read is presented at half rate (s_axi_rvalid is asserted every other clock cycle).
This article is part of the PCI Express Solution Centre
| (Xilinx Answer 34536) | Xilinx Solution Center for PCI Express |
This is a known issue to be fixed in a future release of the core.
To fix the issue in Vivado 2017.4 and 2018.1, please install the respective patches provided in this answer record.
For instructions on installing the patch, please check the instructions in the 'patch_readme' directory in the attached patch file.
Revision History:
05/03/2018 - Initial Release
| 文件名 | 文件大小 | File Type |
|---|---|---|
| AR71052_Vivado_2017_4_preliminary_rev1.zip | 4 MB | ZIP |
| AR71052_Vivado_2018_1_preliminary_rev2.zip | 4 MB | ZIP |
| AR# 71052 | |
|---|---|
| 日期 | 05/03/2018 |
| 状态 | Active |
| Type | 已知问题 |
| IP | |