AR# 71187

描述

How should I connect up the VCU Encoder and Decoder Memory Map ports to the Zynq UltraScale+ MPSoC AFI interfaces?

解决方案

This is dependent on the configuration of the VCU. 

Users should open the VCU GUI and obtain a more precise number for the bandwidth requirements, then configure based on their particular VCU configuration.

Some general Guidelines:

• Each AFI can support up to 16B * 333MHz = 5.3 GB/s.
• User should group like traffic patterns on the AFI to improve efficiency.

The following are example calculations.

The specific bandwidth varies depending on the max resolution and use of the Encoder buffer or Multi-stream configurations. 

• Encoder - The aggregate DRAM Bandwidth for 4Kp60, 4:2:2 10-bit with the encoder buffer is ~3.9GB/s.
• Encoder - The aggregate DRAM Bandwidth for 4Kp60, 4:2:0 8-bit with the encoder buffer is ~2.3GB/s.
• Encoder - The aggregate DRAM Bandwidth for 4Kp60, 4:2:2 10-bit with without the encoder buffer is ~7.6GB/s.
• Encoder - The aggregate DRAM Bandwidth for 4Kp60, 4:2:0 8-bit with without the encoder buffer is ~4.6GB/s.
• Decoder - The aggregate DRMA Bandwidth for 4Kp60, 4:2:2 10-bit is ~6.7GB/s.
• Decoder - The aggregate DRMA Bandwidth for 4Kp60, 4:2:0 8-bit is ~4.3GB/s.

Xilinx recommends that you group like traffic patterns for better efficiency.

For applications using the max resolution, it is recommended that you do a 1:1 mapping of encoder and decoder ports to each AFI, with the combined capture and display traffic using one AFI (traffic class is the same and has a max bandwidth for 4:2:2, 10-bit of ~2.6 GB/s).

This is done in order to avoid saturating the AFI interface.

For example if no encoder buffer is used you would use the following:

• Capture/Display - HP0
• M_AXI_ENC0 - HP1
• M_AXI_ENC1 - HP2
• M_AXI_DEC0 - HP3
• M_AXI_DEC1 - HPC0

However as noted above, when the Encoder buffer is used, the aggregate bandwidth is less than the AFI max, and a user could combine the Encoder interfaces and share a single AFI interface, as shown below:

• Capture/Display - HP0
• M_AXI_ENC0 - HP1
• M_AXI_ENC1 - HP1
• M_AXI_DEC0 - HP2
• M_AXI_DEC1 - HP3

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