This answer record contains the Release Notes and Known Issues for the H.264/H.265 Video Codec Unit and includes the following:
H.264/H.265 Video Codec Unit Page:
https://www.xilinx.com/products/intellectual-property/v-vcu.html
Xilinx Forums:
Please seek technical support via the Video Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
General Information:
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions:
Table 1: Version Table:
This table correlates the core version to the first Vivado design tools release version in which it was included.
| Core Version | Vivado Tools Version | IP Changelog | IP Patches | PetaLinux Features and Bug Fixes | PetaLinux Patches |
|---|---|---|---|---|---|
| v1.2 (Rev. 1) | 2019.2 | (Xilinx Answer 72923) | 2019.2 | (Xilinx Answer 73019) | |
| v1.2 (Rev. 1) | 2019.1 | (Xilinx Answer 72242) | 2019.1 | (Xilinx Answer 72324) | |
| v1.2 | 2018.3 | (Xilinx Answer 71806) | 2018.3 | (Xilinx Answer 71798) | |
| v1.1 (Rev. 1) | 2018.2 | (Xilinx Answer 71212) | (Xilinx Answer 71798) | ||
| v1.1 | 2018.1 | (Xilinx Answer 70699) | (Xilinx Answer 66525) | ||
| v1.0 | 2017.3 | (Xilinx Answer 69903) | (Xilinx Answer 64855) |
Table 2: Silicon Errata
The table below provides Answer Records for VCU Silicon Errata Answer Records.
| Article Number | Article Title |
|---|---|
| (Xilinx Answer 69341) | Decoding An HEVC Video Bitstream With 8K Pixels Per Line With Sample Adaptive Offset (SAO) Filter Enabled Results In Corruption In The Decoded Picture |
| (Xilinx Answer 69340) | Decoding An HEVC Video Bitstream With Level 4 Or 4.1 With Greater Than 4K Pixels Per Line Results In Corruption In The Decoded Picture |
| (Xilinx Answer 69053) | Decoding An 8K CAVLC Video Bitstream can result in Hang |
Table 3: General Guidance
The table below provides Answer Records for general guidance when using the H.264/H.265 Video Codec Unit.
| Article Number | Article Title |
|---|---|
| (Xilinx Answer 70845) | Where can I find an example of using GStreamer AppSrc and AppSink with the Zynq UltraScale+ MPSoC VCU? |
| (Xilinx Answer 71905) | Why do I see the Encoder Write Bandwidth drop to a very small number when setting the B Frame field on the Advanced Tab to STANDARD? |
| (Xilinx Answer 72099) | Why does the AVC use more memory than the HEVC codec? |
| (Xilinx Answer 71801) | Why do I see frame drops when encoding large resolutions or multiple streams? |
| (Xilinx Answer 71677) | Can I use a PS or PL generated clock to drive the VCU reference clock? |
| (Xilinx Answer 71187) | How should I connect up the VCU Encoder and Decoder Memory Map ports to the Zynq UltraScale+ MPSoC AFI interfaces? |
| (Xilinx Answer 71093) | How do I tune the CPB Size and Rate Control parameters? |
| (Xilinx Answer 68361) | Does the VCU support MPEG-2 or VC9 encoding and decoding? |
Known and Resolved Issues:
The following table provides known issues for the H.264/H.265 Video Codec Unit, starting with v1.0, initially released in Vivado 2017.3.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Table 4: IP
| Article Number | Article Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 71182) | Why do see used_port_connected Line 7*, when I place the VCU in a level of hierarchy? | v1.0 | v1.2 |
| (Xilinx Answer 71120) | Why do I see a discrepancy in the units for the Buffer Memory requirements between the GUI and (PG252)? | v1.1 | v1.1 (Rev. 1) |
| (Xilinx Answer 71027) | Why are the Clock Frequencies reported in the VCU_ENC_CLK and VCU_AXI_ENC_CLK registers fixed at 0MHz? | v1.1 | v1.1 (Rev. 1) |
| (Xilinx Answer 71026) | Why does the BVALID fail to de-assert and the BRESP fail to assert when doing back-to-back writes to the VCU, which can result in a VCU hang? | v1.0 | v1.1 (Rev. 1) |
Table 5: Software
For a list of all the PetaLinux Product Update Release Notes and Known Issues see (Xilinx Answer 55776) .
Also see the patches listed above that can be applied to specific releases to resolve some of these known issues found between each release.
| Article Number | Article Title | Version Found |
|---|---|---|
| (Xilinx Answer 73275) | PetaLinux - Zynq UltraScale+ MPSoC VCU - Why Do I see OpenSSL errors when RTMP is enabled in the 2019.1 or 2019.2 VCU TRD in gstreamer1.0-plugins-bad? | 2019.2 |
| (Xilinx Answer 73250) | 2019.2 Zynq UltraScale+ MPSoC VCU - Why do I see frame drops when trying to decode multiple streams (i.e. 20) of input using VCU TRD 2019.2 designs? | 2019.2 |
| (Xilinx Answer 73199) | 2019.2 Zynq UltraScale+ MPSoC VCU - How do I enable support for HDR10 metadata insertion and extraction with VCU Control Software? | 2019.2 |
| (Xilinx Answer 73117) | PetaLinux - Zynq UltraScale+ MPSoC DisplayPort Controller - Why Green Screen on DisplayPort is observed while using VCU TRD multi stream 2019.2 or 2019.1 designs to play a recorded file? | 2019.2 |
| (Xilinx Answer 73051) | 2019.2 Zynq UltraScale+ MPSoC VCU - Why do I see a high decoder latency number while decoding a reduced latency HEVC encoded stream? | 2019.2 |
| (Xilinx Answer 73049) | 2019.2 Zynq UltraScale+ MPSoC VCU - Why are the QP values in the last row not properly updated when using the example GStreamer application? | 2019.2 |
| (Xilinx Answer 73024) | 2019.2 Zynq UltraScale+ MPSoC VCU - Why do I see the VCU hang when encoding 4Kp60 AVC with num-slices=16 using the Xilinx Low Latency mode? | 2019.2 |
| (Xilinx Answer 73023) | 2019.2 Zynq UltraScale+ MPSoC VCU - Why do I see "VCU: unavailable resource error" errors when trying to switch from a 4Kp30 stream to a 4Kp60 stream, using the Xilinx Low Latency mode? | 2019.2 |
| (Xilinx Answer 73022) | 2019.2 Zynq UltraScale+ MPSoC VCU - Why do I see errors when trying to encode 10-bit 4:2:2 4K DCI to HEVC format? | 2019.2 |
| (Xilinx Answer 73021) | 2019.2 Zynq UltraScale+ MPSoC VCU - Why do I see a hang after running two 4kp30 AVC encoding and decoding GStreamer pipelines for more than 12 hours? | 2019.2 |
| (Xilinx Answer 73020) | 2019.2 Zynq UltraScale+ MPSoC VCU - Why do I see a hang while transcoding a Dynamically Changing Resolution stream containing a 4K resolution from AVC or HEVC to AVC using a GStreamer pipeline? | 2019.2 |
| (Xilinx Answer 73274) | 2019.1 Zynq UltraScale+ MPSoC VCU - Why does the VCU decoder crash when trying to read video data from a file in small chunks? | 2019.1 |
| (Xilinx Answer 72958) | 2019.1 Zynq UltraScale+ MPSoC VCU - Why does the VCU Decoder crash when trying to decode two reduced latency streams? | 2019.1 |
| (Xilinx Answer 72734) | 2019.1 Zynq UltraScale+ MPSoC VCU - Why do I occasionally see Zynq UltraScale+ MPSoC VCU OMX Encoder crashes when transitioning out of the recording state? | 2019.1 |
| (Xilinx Answer 72732) | 2019.1 Zynq UltraScale+ MPSoC VCU - Why do I see the Zynq UltraScale+ MPSoC VCU Decoder fail with GET_DMA_PHY: Invalid argument when trying to decode a 1280x960 H.265 stream? | 2019.1 |
| (Xilinx Answer 72605) | 2019.1 Zynq UltraScale+ MPSoC VCU - Why do I see the Zynq UltraScale+ MPSoC VCU Encoder HEVC EnableSkip settings cause encoding to stall after the 600th frame? | 2019.1 |
| (Xilinx Answer 72460) | 2018.3-2019.1 Zynq UltraScale+ MPSoC VCU - Why do I sometimes see heavy APU loading for high bitrate encoding? | 2019.1 |
| (Xilinx Answer 72329) | Why do I get an Out of Memory error when encoding two 4Kp30 HEVC Streams over a long period of time and using the Use Case 2 (UC2) with PL-DDR? | 2019.1 |
| (Xilinx Answer 72328) | 2019.1 Zynq UltraScale+ MPSoC VCU - Why is there initial "jerkiness" when transcoding with a 4Kp60 AVC pipeline? | 2019.1 |
| (Xilinx Answer 72325) | 2019.1 Zynq UltraScale+ MPSoC VCU - Why do I see frame drops or Block Noise for some Use Case 2 (UC2) use cases when PL-DDR is being used? | 2019.1 |
| (Xilinx Answer 72503) | 2018.3 Zynq UltraScale+ MPSoC VCU - How do I improve the quality of the video when using the VCU Encoder to encode video content containing scrolling text? | 2018.3 |
| (Xilinx Answer 72166) | 2018.3 Zynq UltraScale+ MPSoC VCU - Why does the VCU hang when trying to flush multiple times when closing a file? | 2018.3 |
| (Xilinx Answer 72080) | 2018.3 Zynq UltraScale+ MPSoC VCU - Why do I get an error when using GStreamer in reduced latency mode (latency-mode=1) when trying to decode more than 2 streams? | 2018.3 |
| (Xilinx Answer 71993) | 2018.3 Zynq UltraScale+ MPSoC VCU - Why do I see a bitrate of 1.55Mbps when using CBR Rate Control Mode with a Target Bit Rate of 1 Mbps and using a GOP Length of 12? | 2018.3 |
| (Xilinx Answer 71991) | 2018.3 Zynq UltraScale+ MPSoC VCU - Why do I see "blocky" results when decoding non-compliant stream where the max_dec_frame_buffering is larger than the MaxDpbSize? | 2018.3 |
| (Xilinx Answer 71987) | 2018.3 Zynq UltraScale+ MPSoC VCU - Why does the IDR not repeat when the IDR picture frequency is 1 and the GOP Length is 1? | 2018.3 |
| (Xilinx Answer 71934) | 2018.3 Zynq UltraScale+ MPSoC VCU - Why am I getting a "Channel creation failed" error when using the LOW_DELAY_P mode with HEVC multi-stream encoding? | 2018.3 |
| (Xilinx Answer 71871) | 2018.3 Zynq UltraScale+ MPSoC VCU - Why does the VCU produce bad quality output when the LambdaCtrlMode = DYNAMIC_LDA or AUTO_LDA? | 2018.3 |
| (Xilinx Answer 71813) | 2018.3 Zynq UltraScale+ MPSoC VCU - Why does the VCU Control Software Decoder Example application hang while decoding streams which contain errors? | 2018.3 |
| (Xilinx Answer 71812) | 2018.3 Zynq UltraScale+ MPSoC VCU - Why does the VCU Encoder take more time when using CONST_QP mode than it does in VBR mode? | 2018.3 |
| (Xilinx Answer 71811) | 2018.3 Zynq UltraScale+ MPSoC VCU - Why does the VCU Decoder Control Software always output 10-bit data? | 2018.3 |
| (Xilinx Answer 71810) | 2018.3 Zynq UltraScale+ MPSoC VCU - Why does the display freeze after about 10 minutes of decoding and displaying some H.264 streams that are missing the start code in the first NAL unit? | 2018.3 |
| (Xilinx Answer 71809) | 2018.3 Zynq UltraScale+ MPSoC VCU - Why does GStreamer crash when trying to decode some transport stream (TS) files? | 2018.3 |
| (Xilinx Answer 71815) | 2018.2 Zynq UltraScale+ MPSoC VCU - Why do I see the vcu control software fail to release memory after encoding? | 2018.2 |
| (Xilinx Answer 71382) | 2018.1/2 Zynq UltraScale+ MPSoC - Video Codec Unit (VCU) TRD Design Module does not build with PetaLinux SDK generation | 2018.1 |
| (Xilinx Answer 71381) | 2018.1/2 Zynq UltraScale+ MPSoC - Video Codec Unit (VCU) TRD Design Module 3 does not build when using BB_NO_NETWORK (without network) | 2018.1 |
| (Xilinx Answer 71380) | 2018.1 Zynq UltraScale+ MPSoC - Video Codec Unit (VCU) TRD Design Module 3 does not build with PetaLinux DTG | 2018.1 |
| (Xilinx Answer 71253) | 2018.1 Zynq UltraScale+ MPSoC VCU - Why do I get ** (gst-launch-1.0:3316): WARNING **: GopLength should be in multiple of (b-frames + 1). Now setting it to default value? | 2018.1 |
| (Xilinx Answer 71021) | 2018.1 Zynq UltraScale+ MPSoC VCU: Why do I see frame drops at bitrates > 500Mbps when using GStreamer? | 2018.1 |
| (Xilinx Answer 71020) | 2018.1 Zynq UltraScale+ MPSoC VCU - Why does the VCU MCU throw an exception when using multiple streams and Low Latency mode? | 2018.1 |
| (Xilinx Answer 70959) | 2018.1 Zynq UltraScale+ MPSoC VCU: Frame drops are observed with 4kp60fps live source GStreamer pipeline in Linux | 2018.1 |
| (Xilinx Answer 70526) | 2017.4 Zynq UltraScale+ MPSoC - Video Codec Unit (VCU) - Why do I see corruption in the Encoder Buffer when using more than 2 streams? | 2017.4 |
| (Xilinx Answer 70014) | 2017.3 Zynq UltraScale+ MPSoC (VCU): Multi-stream decoder > 4 FULL HD instance fails with memory allocation errors in Linux | 2017.3 |
| (Xilinx Answer 70013) | 2017.3 Zynq UltraScale+ MPSoC (VCU): Frame drops are observed in 4kp60fps transcode use case in Linux | 2017.3 |
Revision History:
| 01/08/2020 | Added (Xilinx Answer 73275), (Xilinx Answer 73274) |
| 12/18/2019 | Added (Xilinx Answer 73117), (Xilinx Answer 73199) and (Xilinx Answer 73250) |
| 11/12/2019 | Added (Xilinx Answer 70845) |
| 10/31/2019 | Added links to PetaLinux Info, Updated formatting and Updated for 2019.2 |
| 10/30/2019 | Added (Xilinx Answer 72958), (Xilinx Answer 72325) and (Xilinx Answer 72329) |
| 10/29/2019 | Added Software Known Issues, |
| 05/15/2019 | Added v1.2 (Rev. 1) to the version Table |
| 03/12/2019 | Added (Xilinx Answer 72099) |
| 01/10/2019 | Added (Xilinx Answer 71905) |
| 12/05/2018 | Added v1.2 to the Version Table and (Xilinx Answer 71801) |
| 10/29/2018 | Added (Xilinx Answer 71677) |
| 09/13/2018 | Added (Xilinx Answer 71187) |
| 06/06/2018 | Added v1.1 (Rev. 1) to the Version Table |
| 05/30/2018 | Added (Xilinx Answer 71182) |
| 05/10/2018 | Added (Xilinx Answer 71120) |
| 05/02/2018 | Added (Xilinx Answer 71026), (Xilinx Answer 71027) and (Xilinx Answer 71093) |
| 04/04/2018 | Added v1.1 to the Version Table |
| 02/07/2018 | Added (Xilinx Answer 69053), (Xilinx Answer 69340) and (Xilinx Answer 69341) |
| 10/26/2017 | Initial Release |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 54490 | Zynq UltraScale+ VCU DDR Controller - Release Notes and Known Issues for Vivado 2018.1 and later versions | N/A | N/A |
| AR# 66763 | |
|---|---|
| 日期 | 01/25/2020 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 | |
| IP | |