Version Found: v4.2
Version Fixed: See (Xilinx Answer 54025)
Starting in Vivado 2018.3, for 7 Series MIG, some configurations have started exhibiting issues.
A "Space" in the project name / directory causes a crash and/or error in Windows 10.
The following error will be seen in the Tcl Console / error log when you try and customize 7 Series MIG (if Vivado does not crash).
ERROR: UNDEF Error in opening fpga xml file C:/Users/<username>/Desktop/upgrade
ERROR: [Common 17-39] 'mig7series_init' failed due to earlier errors.
ERROR: [IP_Flow 19-3475] Tcl error in ::ipgui_design_1_mig_7series_0_0::updateAllModelParams procedure for BD Cell 'mig_7series_0'. ERROR: [Common 17-39] 'mig7series_init' failed due to earlier errors.
INFO: [IP_Flow 19-3438] Customization errors found on 'mig_7series_0'. Restoring to previous valid configuration.
ERROR: [BD 41-245] set_property error - Customization errors found on 'mig_7series_0'. Restoring to previous valid configuration.
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
A 7 Series MIG IP is created or upgraded in Vivado 2018.3. The IP is configured to have 4 controllers (each controller with a x16 interface).
A previously validated pinout/UCF no longer validates. The following error can be seen during validation:
ERROR: Memory port ddr3_cke[0] should not be allocated to pad W13 which is not part of any byte groups of the bank.
A 7 Series MIG IP is created or upgraded in Vivado 2018.3. An invalid pinout is entered during validation.
The user clicks on "Save Log Message," but a Pop-Up appears with the following wording.
The Error message(s) cannot be saved to a log.
A background task is running. Please wait until it completes and try again.
A 7 Series MIG IP (with a custom part) is upgraded to the 2018.3 version. The following critical warning is seen in ip_upgrade.log.
When the 7 Series MIG GUI is customized, the custom part is no longer available as it was lost in the upgrade.
Upgraded port 'ddr3_addr' width 15 differs from original width 16
vector::_M_range_check: __n (which is 0) >= this->size() (which is 0)
ERROR: [IP_Flow 19-3475] Tcl error in ::ipgui_mig_test_bd_mig_7series_0_0::updateAllModelParams procedure for BD Cell 'mig_test_bd_mig_7series_0_0'. vector::_M_range_check: __n (which is 0) >= this->size() (which is 0)
A new 7 Series MIG IP is created in Vivado 2018.3. A custom part is created. A previously validated pinout/UCF no longer validates.
The following error can be seen during validation.
ERROR: All Address/Control ports should be selected in a single bank. Address/Control selected Banks: 14.
To bypass this error and proceed further for design generation, refer to AR #43481
In Vivado 2018.3, 7 Series MIG is issuing VCO DRC's during implementation.
The following error can be seen during validation.
[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 1600.000 MHz (CLKIN1_PERIOD, net pll_clk3) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y1 (cell design_1_i/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1440.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (5.000000), multiplication factor CLKFBOUT_MULT_F (8.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.
These issues will be resolved in the next release of the core.
Please install the attached patch in Vivado 2018.3, following the steps described in the readme file included in the patch zip file.
Revision History:
| 文件名 | 文件大小 | File Type |
|---|---|---|
| AR71898_vivado_2018_3_preliminary_rev4.zip | 30 MB | ZIP |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 54025 | MIG 7 Series - IP Release Notes and Known Issues for Vivado | N/A | N/A |