When I run compile_simlib to compile Vivado simulation libraries for VCS-MX, it fails for the hdmi_gt_controller_v1_0_0 IP.
The error message is as follows.
Error-[ITSFM] Illegal `timescale for module
/vivado/data/ip/xilinx/hdmi_gt_controller_v1_0/hdl/src/verilog/hdmi_gt_controller_v1_0_lib.sv, 19
Module "hdmi_gt_controller_v1_0_0_lib_rst_v1_0" has `timescale but previous
module(s)/package(s) do not.
Please refer LRM 1364-2001 section 19.8.