When targeting a VU19P device with an XDMA IP configured in "DMA" mode, 8.0 GT/s, x4 and "enable descrambler" enabled, the IP hierarchy does not show descrambler modules.
This article is part of the PCI Express Solution Centre
| (Xilinx Answer 34536) | Xilinx Solution Center for PCI Express |
This is a known issue in VU19P devices only, to be fixed in a future version of the core. See (Xilinx Answer 65443) for the latest status on known issue fixes.
To fix the issue in Vivado 2020.1, install the patch attached to this Answer Record.| 文件名 | 文件大小 | File Type |
|---|---|---|
| AR75799_Vivado_2020_1_preliminary_rev1.zip | 1 MB | ZIP |
| AR# 75799 | |
|---|---|
| 日期 | 11/30/2020 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| Tools | |
| IP | |