Memory Interfaces Design Hub - UltraScale DDR3/DDR4 Memory

Introduction	Date
XTP359 - Memory Interface UltraScale Design Checklist
PG150 - UltraScale Architecture FPGAs Memory IP Product Guide	08/11/2021
PG150 - Creating a Memory Interface Design using Vivado MIG	08/11/2021
Designing with UltraScale Memory IP	09/16/2014
AR58435 - Memory Interface UltraScale IP Release Notes	03/31/2021
Supported Memory Interfaces and Data Rates
Design Requirements	Date
PG150 - Input Clock Guidelines	08/11/2021
Memory Interface External Clocking	03/15/2016
UG583 - PCB Guidelines for DDR4 SDRAM	06/03/2021
UG583 - PCB Guidelines for DDR3 SDRAM	06/03/2021
PG150 - DDR4 Pin Rules	08/11/2021
PG150 - DDR3 Pin Rules	08/11/2021
UG899 - I/O Planning for UltraScale Device Memory IP	06/16/2021
PG150 - Designing for High Efficiency	08/11/2021
PG150 - Calculating User Specified Pattern Efficiency Using the Memory IP Performance Testbench	08/11/2021
Designing with UltraScale Memory IP	09/16/2014
UG899 - Importing I/O Ports for an Existing Pin-Out/Board	06/16/2021
Interfacing to Memory Interface IP	Date
PG150 - Interfacing to the Memory IP User Interface	08/11/2021
PG150 - Interfacing to the PHY Only Interface	08/11/2021
PG150 - Interfacing to the AXI4 Slave Interface	08/11/2021
Simulating Memory Interface IP	Date
PG150 - Simulating the Memory IP Example Design	08/11/2021
DH0010 - Vivado Logic Simulation Design Hub	06/16/2021
Frequently Asked Questions (FAQ)	Date
AR62920 - Memory IP UltraScale Solution Center - Frequently Asked Questions (FAQ)

User Guides	Date
UG583 - UltraScale Architecture PCB Design Guide	06/03/2021
UG571 - UltraScale Architecture SelectIO Resources User Guide	08/28/2019
UG572 - UltraScale Architecture Clocking Resources User Guide	08/28/2020
Vivado Design Hubs	Date
DH0007 - I/O and Clock Planning	06/16/2021
DH0003 - Designing with IP	06/16/2021
DH0009 - Using IP Integrator	06/16/2021
Memory Interface Design Tips	Date
PG150 - Migrating Memory IP Using Vivado	08/11/2021
UG583 - PCB Trace Derating	06/03/2021
PG150 - Using the Memory IP Traffic Generator	08/11/2021
Targeted Reference Designs	Date
DH0043 - Kintex UltraScale FPGA KCU105 Evaluation Kit	06/16/2021

Please visit the Xilinx Service Portal to open or review a service request.

Solution Centers	Date
AR34243 - Xilinx Memory IP Solution Center	04/26/2016
Design Advisories	Date
AR33566 - Design Advisories for Memory Interfaces	08/25/2020
Known Issues	Date
AR73052 - UltraScale/UltraScale+ DDR3/DDR4 IP - [Mig 66-119] Phy Core Regeneration & Stitching Failed	06/11/2020
AR69035 - DDR4 UltraScale and UltraScale+ IP Release Notes and Known Issues	03/31/2021
AR69036 - DDR3 UltraScale and UltraScale+ IP Release Notes and Known Issues	03/31/2021
Debug Resources	Date
PG150 - Using the Memory Interface Debug GUI and XSDB for Calibration Failures	08/11/2021
PG150 - Debugging Data Errors	08/11/2021
XTP359 - Memory Interface UltraScale Design Checklist
AR62181 - Hardware Debug Guide - Debugging Memory Interface Issues
Forums	Date
Xilinx User Community Forums - Memory Interface Generator (MIG)

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