RFSoC 2x2 Kit
RFSoC 2x2 Kit
Xilinx’s Radio Frequency System-on-Chip (RFSoC) devices have created a new class of integrated circuit architecture for the communications and instrumentation markets. RFSoCs combine high-accuracy ADCs and DACs operating at Giga samples per second with programmable heterogeneous compute engines.
XUP is offering the RFSoC 2x2 kit exclusively for academic customers. The kit features:
- $2,149* available only to academic customers
- RFSoC 2x2 board with 2 RF DAC and 2 RF ADC channels
- PYNQ framework with Jupyter Lab for exceptional ease-of-use
- Open-source resources including teaching materials, notebooks, and design examples
- Complete end-to-end reference designs including spectrum analyzers and software defined radios
- Dedicated project webpage at rfsoc-pynq.io
- GitHub-hosted repositories of all project materials
- Online community support forum
*12 July 2021: The price has been updated due to substantial increases in component costs which have been widespread across the industry. This has added significant cost to the RFSoC 2x2. The impact on the price has been minimized with support from Xilinx and other board partners.
What is included?
- RFSoC 2x2 Board
- 12V 72W power supply unit
- USB 3.0 A to Micro B Cable
- 2 RF cables with SMA
connectors
- 16 GB MicroSD card with pre-loaded Linux and PYNQ image
RFSoC 2x2 Board Key Features
| Feature | Description |
| FPGA |
|
| I/O Interfaces |
|
| Memory |
|
| Switches and LEDs | Connected to the programmable logic IO
Connected to the processor system
|
| Clock sources |
|
| Expansion ports |
|
| Power Monitoring |
|
Zynq UltraScale+ RFSoC XCZU28DR Key Features
- 64-bit Quad ARM® Cortex™-A53 MPCore™ and dual-core ARM Cortex-R5F with CoreSight™
- 32 KB Instruction, 32 KB Data per processor L1 Cache in APU
- 1 MB unified L2 Cache in APU
- 32 KB Instruction, 32 KB Data per processor L1 Cache and TCM in RPU
- 256 KB On-Chip Memory w/ECC
- UART, CAN 2.0B, I2C, SPI, 128b GPIO
- USB 2.0/3.0, Tri-mode Gigabit Ethernet, SD/SDIO 3.0 on-chip peripherals
- Display Port, SATA
- 930K system logic cells
- 60.5 MB of fast on-chip RAM
- 4,272 DSP slices
- 16 33G Transceivers
- 8 12-bit 4.096 GSPS RF-ADC (2 of which are available on the RFSoC 2x2)
- 8 14-bit 6.554 GSPS RF-DAC (2 of which are available on the RFSoC 2x2)
- 32-bit and 64-bit bus width support for DDR4, DDR3, DDR3L, or LPDDR3 memories, and 32-bit bus width support for LPDDR4 memory
| PYNQ Image | The RFSoC PYNQ image is a bootable Linux image, and includes the pynq Python package, and other open-source packages. It contains RFSoC-based design and application support. |
| Vivado Design Suite:System Edition | The Xilinx Vivado® Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for devices. You can use either Design Edition or System Edition to update the base overlay or create a new overlay. The WebPack edition does not support the device of the board. The supported board files are available at the XilinxBoardStore GitHub repository. |
Additional Information and Supporting Material
- Please visit the RFSoC PYNQ project webpage
- Video presentation on RFSoC 2x2 Kit at the FPGA2021 conference is available at http://www.rfsoc-pynq.io/tutorial.html
How to purchase at the academic price?
In order to purchase the kit at the academic price, you will need to:
- Be a full-time member of staff at an accredited academic institution
- Enroll in the XUP Program if you have not done so yet
- Fill out the form describing your RF teaching or research project
Once the request is approved, you and HTG will be notified with directions to purchase the kit.