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XUP PYNQ-Z1

Overview

PYNQ- Python Productivity for Zynq

PYNQ is an open-source project from Xilinx that makes it easy to design embedded systems with Zynq Systems on Chips (SoCs). Using the Python language and libraries, designers can exploit the benefits of programmable logic and microprocessors in Zynq to build more capable and exciting embedded systems.

What is included?

  • The PYNQ-Z1 board featuring the ZYNQ XC7Z020-1CLG400C SoC

Additional Required Items

  • The pynq image and 8 GB SD Card
  • Micro-USB cable 
  • Ethernet cable 

Zynq-7000 SoC Features

  • Dual ARM® Cortex™-A9 MPCore™ with CoreSight™
  • 32 KB Instruction, 32 KB Data per processor L1 Cache
  • 512 KB unified L2 Cache
  • 256 KB On-Chip Memory
  • 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
  • 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO on-chip peripherals
  • 85K logic cells (13300 logic slices, each with four 6-input LUTs and 8 flip-flops)
  • 630 KB of fast block RAM
  • Four clock management tiles, each with phase-locked loop (PLL)
  • 220 DSP slices
  • Internal clock speeds exceeding 450MHz
  • 2x 12 bit, 1 MSPS On-chip analog-to-digital converter (XADC)
Hardware

Key Features

Feature Description
FPGA
  • Zynq-7000 SoC XC7Z020-1CLG400C
I/O Interfaces
  • USB-JTAG Programming circuitry
  • USB OTG 2.0
  • USB-UART bridge
  • One 10/100/1G Ethernet
  • HDMI Input
  • HDMI Output
  • Electret microphone with pulse density modulated (PDM) output
  • 3.5mm mono audio output jack, pulse-width modulated (PWM) format
Memory
  • 512 Mbyte DDR3
  • 128 Mbit Quad-SPI Flash
  • Micro SD card connector
Switches and LEDs
  • 2 Slide switches 
  • 2 RGB LEDs 
  • 4 LEDs
  • 4 Push-buttons 
Clocks
  • One 125 MHz for PL
  • One 50 MHz for PS
Expansion ports
  • 2 Pmod ports
  • 1 Arduino Shield
  • 16 GPIO
  • 6 Single-ended 0-3.3V Analog inputs to XADC
  • 4 Differential 0-1.0V Analog inputs to XADC
Tools & IP
Download PYNQ Image The PYNQ image is a bootable Linux image, and includes the pynq Python package, and other open-source packages.
Vivado Design Suite: WebPack Edition The Xilinx Vivado® Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for devices. One of the editions, WebPACK™, is FREE to download and provides access to Vivado features and functionality at no cost. It can be used to update the base overlay or create a new overlay.
Docs & Designs

Documentation

Additional Information and Supporting Material