Partial Reconfiguration Flow using ISE

After completing this workshop, you will be able to:

• Understand the basic terminologies used in partial reconfiguration
• List the fundamental steps involved in developing a design capable of partial reconfiguration
• Learn capabilities of and restrictions imposed by the reconfiguration tools
• Use Xilinx EDK, Software Development Kit (SDK), and PlanAhead tools to design and develop a partial reconfiguration capable designs

Day 1:

• Introduction to Partial Reconfiguration
• Introduction to PlanAhead
• Lab 1: Introduction to Partial Reconfiguration Design Flow
  • Step-by-step introduction to the partial reconfiguration design flow using PlanAhead tool and pre-build design.  Verify the functionality using iMPACT program to fully- and partially- configure the FPGA.
• Design Considerations including Partitioning and Clocking
• Timing Constraints and Analysis
• Lab 2: Apply Timing Constraints and Perform Analysis
  • Synthesize some of the modules using Xilinx Synthesis Technology (XST). Floorplan the design, create timing constraints, and implement the design. Back annotate the results and perform analysis. Verify the functionality using iMPACT program to fully and partially configure the FPGA.
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• Introduction to EDK
• Design Considerations involved in Defining Reconfigurable Peripheral
• Lab 3: Reconfigure using Xilinx Platform Studio (XPS) XPS Hardware Internal Configuration Access Port (HWICAP) pcore
  • Create a processor-based application capable of reconfiguring a peripheral using XPS HWICAP pcore and partial bitstreams stored on a compact flash card.  The full configuration takes place using the system ace controller. The partial reconfiguration takes place under user application control.

Day 2:

• Design Considerations in Driving ICAP from User's Logic
• Debugging Partial Reconfiguration Designs using ChipScope™ software
• Lab 4: Driving ICAP from User Logic and Debugging using ChipScope
  • Use ICAP associated logic to perform partial reconfiguration.  The provided logic eliminates use of a processor system to perform partial reconfiguration.  Debug the design using ChipScope.
• Designing a Reconfigurable FSL Peripheral
• Lab 5: Reconfigure a Fast Simplex Link (FSL) Peripheral from Flash Memory
  • Design a processor system having a FSL peripheral which will be reconfigured using partial bitstreams stored in a flash memory    
• Designing with a System Generator Core
• Lab 6: Reconfigurable Audio Filters
  • Use audio filter cores generated in System Generator to develop a reconfigurable system providing various filtering capabilities.