Converts Avalon Master Endpoints to AXI for seamless interconnection and integration
Product Description
The Xilinx® LogiCORE™ AMM Master Bridge IP core translates Avalon Master endpoints to AXI Masters. This IP allows parameter configuration to match Avalon Master endpoint properties and enables seamless interface to AXI.
Key Features and Benefits
- AXI4 and AXI4-Lite Compliant
- Supports up to 1024-bit data width AXI4-Memory Map interface
- Supports 32-bit data width for AXI4-Lite interface
- Support for Fixed and Variable Wait
- Support for Fixed and Variable Latency
Resource Utilization
Support
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