AR# 33289

描述

解决方案

Changes to the Samsung model (K7SXXXXT4C_R04.v) are required for proper simulation operation with the Virtex-6 FPGA QDRII+ design. Edit the following within the model:

Line 244 -

Change from: eclk = ~K_N;

Change to: eclk = ~K;

Line 245 -

Change from: eclk_b = ~K;

Change to: eclk_b = ~K_N;

This ensures data is presented on the correct clock. After making these changes, calibration completes successfully.

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