2. 技术支持
  3. AR# 3674: ** OBSOLETE ** V1.4.0 COREGEN: Can v1.4.0 be installed over the Alpha 3.0.x release?
  4. AR# 36749: Design Assistant for PCI Express - Simulation Questions Regarding Transaction Layer Traffic

AR# 36749

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Design Assistant for PCI Express - Simulation Questions Regarding Transaction Layer Traffic

描述

This Answer Record identifies starting points to debug transaction layer related questions in simulation. However, much of this information is also true in hardware, but is more prevalent in simulation sincethecore generates the rootport simulation model for you.

NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

解决方案


For information on why TLPs might not show up on the user application interface, see (Xilinx Answer 36750). This applies to both root port and endpoint applications.
For information on why TLPs might get corrupted at the MIM interface, see (Xilinx Answer 37752). This applies to both root port and endpoint applications.
Revision History
09/01/2010 - Added (Xilinx Answer 37752)
08/13/2010 - Initial Release

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
38548 Design Assistant for PCI Express - Simulation Traffic Questions N/A N/A
37752 Design Assistant for PCI Express - Issues in simulation when user inputs are perfectly aligned to trn_clk or user_clk_out N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A
AR# 36749
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
IP
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