AR# 37472

MIMRXWEN

MIMRXWADDR

MIMRXWDATA

MIMRXREN

MIMRXRADDR

MIMRXRDATA

The "W" and the "R" in the names indicate "write" and "read," respectively.

The "EN" in the names indicates an enable for the BRAM.

The "ADDR" in the names indicates the address of the BRAM.

The "DATA" in the names indicates the data in the BRAM that is being read from or written to.

The "DATA" bus will contain the TLP.

The DATA and ADDR on the "write" side of the BRAM will be aligned to the "WEN" signal.

The DATA on the "read" side of the BRAM will come out of the BRAM two clock cycles after the "REN" signal.

Depending on the device, there may be additional bits appended to the MIM***DATA bus. The bits that are appended can be ignored. The valid TLP data on the MIM***DATA bus will always be either 1DW or 2DW. The upper bits resulting in a greater than 1 or 2 DW length can be ignored.

The figure below shows a Completion with Data of 1 DW on the transmit MIM interface. There data width is 64 bits or 2 DW with no extra bits appended.

The figure below shows a Completion with Data of 1 DW on the transmit MIM interface. The data width is 64 bits or 2 DW with 4 extra bits appended. The '9' at address x324 should be ignored and the 1 at address x325 should be ignored.

By default, the MIM interface acts as a fill-and-spill interface. This means that an entire TLP is written to the MIM interface before it is read from. Virtex-6 and Spartan-6 FPGA allow you to improve the latencyby using the streaming mode (cut-through) feature on the transmit interface. Instreaming mode, theintegrated blockstarts reading the TLP out of the BRAM and sendingit on to the link before the user finishes transmitting the full packet into the BRAM.For more information on streaming mode, please refer to the appropriate user guide(Xilinx Answer 35920).

The figure below shows the flow of a packet going through our receiving MIM interface and ending up at the TRN interface.