13.4 Resolved Issues
| (Xilinx Answer 44089) | Kintex-7 GTX IBERT - The RX Equalization label is incorrect and should be called Termination Voltage |
| (Xilinx Answer 43548) | ChipScope 13.2- When running the core inserter flow the following error is seen in MAP - ERROR:TSDatabase:19 |
| (Xilinx Answer 42757) | Virtex-7, Kintex-7, 13.2, 13.3 - GTX IBERT-"ERROR:Bitgen:342" Occurs During Bitstream Generation of GTX IBERT core |
| (Xilinx Answer 44191) | 13.3:Kintex-7/Virtex-7 - ChipScope IBERT - Using the KC705 or VC707 Board Configuration Settings file causes implementation error |
| (Xilinx Answer 44628) | 13.3, Virtex-7, GTX IBERT - Channel 3 of GTX_QUAD must be connected when using Quad Based Protocol selection or asynchronous operation will fail |
| (Xilinx Answer 44649) | Kintex-7, 13.3 - GTX IBERT - QPLL Locked status is not getting updated periodically which may result in false reading |
| (Xilinx Answer 44648) | Kintex-7, 13.3 - IBERT GTX - QPLLREFCLKSEL always selects REFCLK0 |
| (Xilinx Answer 44801) | Virtex-6, 13.3, GTX IBERT - Right side GTX transceivers do not link |
| (Xilinx Answer 44879) | Kintex-7, 13.3, GTX IBERT - "ERROR:sim - Failed to generate ASY schematic symbol." |
| (Xilinx Answer 44963) | Virtex-6 CXT, 13.3, GTX IBERT - IBERT GUI in CORE Generator tool does not launch if project option is set to CX75T |
| (Xilinx Answer 45123) | 13.3 Kintex-7, Virtex-7 ChipScope GTX IBERT - RXDFELPMRESET_TIME set incorrectly |
| (Xilinx Answer 45097) | 13.2, 13.3 Kintex-7 GTX IBERT - Designs with multiple reference clocks fail if different clock sources are used |
| (Xilinx Answer 44881) | Spartan-6, 13.4 and earlier, GTP IBERT - TX Diff Output Swing values in Analyzer do not match GTP Users Guide values |
| (Xilinx Answer 44663) | Virtex-6, 13.3 and 13.4, GTX IBERT - Unchecking "Generate Bitstream" option causes generation of core to fail |
| (Xilinx Answer 44645) | 13.3 and 13.4, Virtex-6, ML605 - GTX IBERT - "ml605 bank113fmchpc" Board Configuration Setting sets refclk incorrectly |
13.4 Known Issues for ChipScope Pro:
| (Xilinx Answer 43903) | ChipScope - Core Inserter freezes after going to ILA parameters page due to "java.lang.OutOfMemoryError" error |
| (Xilinx Answer 41262) | 13.x ChipScope, CORE Generator - upgrade cores fails when 7 Series part is selected |
| (Xilinx Answer 42856) | 13.x ChipScope Pro Analyzer - Clean Previous Project Settings applies to all devices in JTAG chain |
| (Xilinx Answer 44190) | 13.x:ChipScope Pro - ATC2 Core - CRITICAL WARNING: Could not resolve non-primitive black box cell 'OPAD' |
| (Xilinx Answer 45218) | 13.x - ChipScope Analyzer: Net names not getting properly imported when CDC and bit file are located in a directory with spaces |
13.4 Known Issues for ChipScope IBERT:
| (Xilinx Answer 43747) | Kintex-7 IBERT GTX (13.2 and later) - Core allows some unsupported Line Rates with QPLL for Initial ES silicon |
| (Xilinx Answer 42464) | Kintex-7, ChipScope Pro - IBERT (13.2 and Later) - Kintex-7 Core Limitations and Support for Early Silicon |
| (Xilinx Answer 44664) | Virtex-5 GTP - 1Gbps line rate does not work when targeting Virtex-5 LX20T device |
| (Xilinx Answer 44624) | Virtex-5, GTP/GTX IBERT Core Generator - IBERT sweep test of PREEMPHASIS does not work |
| (Xilinx Answer 45381) | 45381 - ChipScope GTX IBERT, Virtex-5 FXT/TXT- Performing a sweep test on DFETAP values doesn't work correctly |
| (Xilinx Answer 45648) | 13.1, 13.2, 13.3, 13.4 - Virtex-7/Kintex-7 - Using KC705 or VC705 "Board Configuration Setting" in GTX IBERT uses incorrect IO Standard for system clock |
| (Xilinx Answer 45674) | 13.4 and earlier - Virtex-7 and Kintex-7 - GTX IBERT core with 562.5MHz refclk may cause map error |
| (Xilinx Answer 45656) | 13.4 - Kintex-7 - GTX IBERT - QPLL won't lock at 8Gbps line rate when using General ES silicon |
13.3 Resolved Issues
| (Xilinx Answer 42837) | 13.2 ChipScope IBERT - Default line rate setting for board configuration setting is invalid rate |
| (Xilinx Answer 42839) | 13.2 Kintex-7 GTX IBERT - TXOUT_DIV and RXOUT_DIV set to incorrect values when line rate = 3.125 Gbps |
| (Xilinx Answer 42841) | Virtex-6 GTX IBERT - How to enable DIFF_TERM on the system clock in the IBERT core |
| (Xilinx Answer 42843) | Virtex-6 GTX IBERT - Some QUADs must always be instantiated for GTs to work correctly |
| (Xilinx Answer 42857) | Kintex-7 GTX IBERT - Using internal system clock source causes error in BitGen |
| (Xilinx Answer 43259) | 13.x Virtex-6 GTH IBERT - Problems running half rate speed with the IBERT core |
| (Xilinx Answer 43753) | ChipScope Analyzer - Long signal names are truncated when exporting waveforms to PDF |
| (Xilinx Answer 43894) | 13.2 ChipScope, Virtex-6 GTX IBERT - "ERROR:Place:1145" Unroutable placement error when generating the core |
| (Xilinx Answer 43958) | 13.2 ChipScope Pro - Inserter Fails when Targeting a Virtex-7 Device |
| (Xilinx Answer 44133) | 13.2 Virtex-6 HXT GTH IBERT - Changing the value of RXRATE and TXRATE does not change the line rate |
13.3 Known Issues for ChipScope Pro:
| (Xilinx Answer 43903) | ChipScope - Core Inserter freezes after going to ILA parameters page due to "java.lang.OutOfMemoryError" error |
| (Xilinx Answer 43548) | ChipScope 13.2 When running the core inserter flow the following error is seen in MAP - ERROR:TSDatabase:19 |
| (Xilinx Answer 41262) | 13.x ChipScope, CORE Generator - upgrade cores fails when 7-series part is selected |
| (Xilinx Answer 42856) | 13.x ChipScope Pro Analyzer - Clean Previous Project Settings applies to all devices in JTAG chain |
| (Xilinx Answer 44190) | 13.3:ChipScope Pro - ATC2 Core - CRITICAL WARNING: Could not resolve non-primitive black box cell 'OPAD' |
| (Xilinx Answer 45218) | 13.1, 13.2, 13.3 - ChipScope Analyzer: Net names not getting properly imported when CDC and bit file are located in a directory with spaces |
| (Xilinx Answer 45657) | 13.3 - Spartan-6 - ChipScope Pro Inserter - ERROR:encore:175 when using WebPACK |
13.3 Known Issues for ChipScope IBERT:
| (Xilinx Answer 44089) | Kintex-7 GTX IBERT - The RX Equalization label is incorrect and should be called Termination Voltage |
| (Xilinx Answer 43747) | Kintex-7 IBERT GTX (13.2 and later) - Core allows some unsupported Line Rates with QPLL for Initial ES silicon |
| (Xilinx Answer 42464) | 13.2 ChipScope Pro IBERT - Kintex-7 core limitations and support for 1.0 and 1.1 Silicon |
| (Xilinx Answer 44065) | Kintex-7 GTX IBERT - what does the silicon version drop down menu mean? |
| (Xilinx Answer 42757) | Virtex-7, Kintex-7, 13.2, 13.3 - GTX IBERT-"ERROR:Bitgen:342" Occurs During Bitstream Generation of GTX IBERT core |
| (Xilinx Answer 44191) | 13.3:Kintex-7/Virtex-7 - ChipScope IBERT - Using the KC705 or VC707 Board Configuration Settings file causes implementation error |
| (Xilinx Answer 44645) | 13.3 and 13.4, Virtex-6, ML605 - GTX IBERT - "ml605 bank113fmchpc" Board Configuration Setting sets refclk incorrectly |
| (Xilinx Answer 44628) | 13.3, Virtex-7, GTX IBERT - Channel 3 of GTX_QUAD must be connected when using Quad Based Protocol selection or asynchronous operation will fail |
| (Xilinx Answer 44649) | Kintex-7, 13.3 - GTX IBERT - QPLL Locked status is not getting updated periodically which may result in false reading |
| (Xilinx Answer 44648) | Kintex-7, 13.3 - IBERT GTX - QPLLREFCLKSEL always selects REFCLK0 |
| (Xilinx Answer 44663) | Virtex-6, 13.3, GTX IBERT - Unchecking "Generate Bitstream" option causes generation of core to fail |
| (Xilinx Answer 44664) | Virtex-5 GTP - 1Gbps line rate does not work when targeting Virtex-5 LX20T device |
| (Xilinx Answer 44624) | Virtex-5, GTP/GTX IBERT Core Generator - IBERT sweep test of PREEMPHASIS does not work |
| (Xilinx Answer 44801) | Virtex-6, 13.3, GTX IBERT - Right side GTX transceivers do not link |
| (Xilinx Answer 44879) | Kintex-7, 13.3, GTX IBERT - "ERROR:sim - Failed to generate ASY schematic symbol." |
| (Xilinx Answer 44881) | Spartan-6, 13.2 and 13.3, GTP IBERT - TX Diff Output Swing values in Analyzer do not match GTP Users Guide values |
| (Xilinx Answer 44963) | Virtex-6 CXT, 13.3, GTX IBERT - IBERT GUI in CORE Generator tool does not launch if project option is set to CX75T |
| (Xilinx Answer 45123) | 13.3 Kintex-7, Virtex-7 ChipScope GTX IBERT - RXDFELPMRESET_TIME set incorrectly |
| (Xilinx Answer 45097) | 13.2, 13.3 Kintex-7 GTX IBERT - Designs with multiple reference clocks fail if different clock sources are used |
| (Xilinx Answer 45381) | 45381 - ChipScope GTX IBERT, Virtex-5 FXT/TXT- Performing a sweep test on DFETAP values doesn't work correctly |
| (Xilinx Answer 45646) | 13.1, 13.2, 13.3 - Kintex-7/Virtex-7 - GTX IBERT will not work when using 32-bit DATA_WIDTH |
| (Xilinx Answer 45648) | 13.1, 13.2, 13.3, 13.4 - Virtex-7/Kintex-7 - Using KC705 or VC705 "Board Configuration Setting" in GTX IBERT uses incorrect IO Standard for system clock |
| (Xilinx Answer 45674) | 13.4 and earlier - Virtex-7 and Kintex-7 - GTX IBERT core with 562.5 MHz refclk may cause map error |
13.2 Resolved Issues:
| (Xilinx Answer 40486) | 13.1 ChipScope Pro IBERT - Generation fails at NGDBuild with "ERROR:NgdBuild:604" and "ERROR:NgdBuild:456" |
| (Xilinx Answer 39512) | 12.x/13.x ChipScope IBERT GTH - "ERROR:sim - runPar : IBERT:par: Timing for this design was not met..." |
| (Xilinx Answer 40811) | 13.1 ChipScope, PlanAhead - "WARN: [HD-Tcl 3] No nets matched '<connect_debug_port cs_ila_0_0/TRIG0 [get_nets -match_style ucf {module_name\/net_name} ] WARN: [HD-Tcl 3] No n>'. ERROR: Invalid value for 'nets'" |
| (Xilinx Answer 40855) | 12.x/13.1 ChipScope IBERT - Virtex-6 GTX attribute TERMINATION_OVRD set incorrectly to TRUE |
| (Xilinx Answer 41734) | 12.x/13.1 ChipScope IBERT - Virtex-6 GTH Transceivers Production Silicon Support |
| (Xilinx Answer 39660) | 13.1 and earlier - ChipScope Inserter is reporting inaccurate block RAM count for certain devices |
13.2 Known Issues for ChipScope Pro:
| (Xilinx Answer 42856) | 13.x ChipScope Pro Analyzer - Clean Previous Project Settings applies to all devices in JTAG chain |
| (Xilinx Answer 41262) | 13.x ChipScope, CORE Generator - upgrade cores fails when 7-series part is selected |
| (Xilinx Answer 43548) | ChipScope 13.2 When running the core inserter flow the following error is seen in MAP - ERROR:TSDatabase:19 |
| (Xilinx Answer 43753) | ChipScope Analyzer - Long signal names are truncated when exporting waveforms to PDF |
| (Xilinx Answer 43894) | 13.2 ChipScope, Virtex-6 GTX IBERT - "ERROR:Place:1145" Unroutable placement error when generating the core |
| (Xilinx Answer 43958) | 13.2 ChipScope Pro - Inserter Fails when Targeting a Virtex-7 Device |
| (Xilinx Answer 43903) | ChipScope - Core Inserter freezes after going to ILA parameters page due to "java.lang.OutOfMemoryError" error |
| (Xilinx Answer 44279) | 13.2 ChipScope Inserter - Fails to accept data depth more than 8192 |
| (Xilinx Answer 45218) | 13.1, 13.2, 13.3 - ChipScope Analyzer: Net names not getting properly imported when CDC and bit file are located in a directory with spaces |
13.2 Known Issues for ChipScope IBERT:
| (Xilinx Answer 42757) | 13.2 IBERT - "ERROR:Bitgen:342 occurs during bitgen of Kintex-7 IBERT" |
| (Xilinx Answer 42464) | 13.2 ChipScope Pro IBERT - Kintex-7 core limitations and support for 1.0 and 1.1 Silicon |
| (Xilinx Answer 42837) | 13.2 ChipScope IBERT - Default line rate setting for board configuration setting is invalid rate |
| (Xilinx Answer 42839) | 13.2 Kintex-7 GTX IBERT - TXOUT_DIV and RXOUT_DIV set to incorrect values when line rate = 3.125 Gbps |
| (Xilinx Answer 42841) | Virtex-6 GTX IBERT - How to enable DIFF_TERM on the system clock in the IBERT core |
| (Xilinx Answer 42843) | Virtex-6 GTX IBERT - Some QUADs must always be instantiated for GTs to work correctly |
| (Xilinx Answer 42857) | Kintex-7 GTX IBERT - Using internal system clock source causes error in BitGen |
| (Xilinx Answer 43259) | 13.x Virtex-6 GTH IBERT - Problems running half rate speed with the IBERT core |
| (Xilinx Answer 43747) | 13.2 Kintex-7 IBERT GTX - Core allows some unsupported Line Rates with QPLL for Initial ES silicon |
| (Xilinx Answer 44089) | Kintex-7 GTX IBERT - The RX Equalization label is incorrect and should be called Termination Voltage |
| (Xilinx Answer 44133) | 13.2 Virtex-6 HXT GTH IBERT - Changing the value of RXRATE and TXRATE does not change the line rate |
| (Xilinx Answer 44881) | Spartan-6, 13.2 and 13.3, GTP IBERT - TX Diff Output Swing values in Analyzer do not match GTP Users Guide values |
| (Xilinx Answer 45097) | 13.2, 13.3 - Kintex-7 GTX IBERT - Designs with multiple reference clocks will fail if different clock sources are used |
| (Xilinx Answer 45381) | 45381 - ChipScope GTX IBERT, Virtex-5 FXT/TXT- Performing a sweep test on DFETAP values doesn't work correctly |
| (Xilinx Answer 45646) | 13.1, 13.2, 13.3 - Kintex-7/Virtex-7 - GTX IBERT will not work when using 32-bit DATA_WIDTH |
| (Xilinx Answer 45648) | 13.1, 13.2, 13.3, 13.4 - Virtex-7/Kintex-7 - Using KC705 or VC705 "Board Configuration Setting" in GTX IBERT uses incorrect IO Standard for system clock |
| (Xilinx Answer 45674) | 13.4 and earlier - Virtex-7 and Kintex-7 - GTX IBERT core with 562.5MHz refclk may cause map error |
13.1 Known Issues for ChipScope Pro:
| (Xilinx Answer 40549) | 13.1 ChipScope Pro Analyzer - Import dialog shows "Save" when importing settings |
| (Xilinx Answer 39647) | 12.x/13.1 ChipScope - ChipScope core generation when directory names are too long |
| (Xilinx Answer 39238) | 12.x/13.1 ChipScope ILA - Timing error found in Unconstrained Path report in ChipScope core |
| (Xilinx Answer 40693) | 13.x/12.x ChipScope - maximum data depth setting for Spartan-6 in ILA |
| (Xilinx Answer 40811) | 13.1 ChipScope, PlanAhead - "WARN: [HD-Tcl 3] No nets matched '<connect_debug_port cs_ila_0_0/TRIG0 [get_nets -match_style ucf {module_name\/net_name} ] WARN: [HD-Tcl 3] No n>'. ERROR: Invalid value for 'nets'" |
| (Xilinx Answer 45218) | 13.1, 13.2, 13.3 - ChipScope Analyzer: Net names not getting properly imported when CDC and bit file are located in a directory with spaces |
| (Xilinx Answer 39660) | 13.1 and earlier - ChipScope Inserter is reporting inaccurate block RAM count for certain devices |
13.1 Known Issues for ChipScope IBERT:
| (Xilinx Answer 40486) | 13.1 ChipScope Pro IBERT - Generation fails at NGDBuild with "ERROR:NgdBuild:604" and "ERROR:NgdBuild:456" |
| (Xilinx Answer 40547) | 13.1 ChipScope IBERT - When generating an IBERT Virtex-6 GTX core I see the following messages - "ERROR:sim - Unable to evaluate Tcl command: ::xilinx::sim::generation::generatePsfCore {chipscope_ibert_Virtex_gtx_v2_05_a} {chipscope_ibert} {ALL}" |
| (Xilinx Answer 39756) | 12.4/13.x ChipScope IBERT - How do I set the Virtex-6 GTH Transceivers in near-end PMA loopback? |
| (Xilinx Answer 39125) | 12.4/13.1 Virtex-6 GTX IBERT - TX output swing lower than User Guide and Characterization Report |
| (Xilinx Answer 40855) | 12.x/13.1 ChipScope IBERT -Virtex-6 GTX attribute TERMINATION_OVRD set incorrectly to TRUE |
| (Xilinx Answer 39871) | 12.x/13.x ChipScope Pro IBERT, Virtex-5 GTX - Core is not recognized by CS analyzer - UNIT:1_0 Unsupported (XSDB-512) |
| (Xilinx Answer 41838) | 13.x ChipScope IBERT GTH - ChipScope Analyzer appears to hang or shows "ERROR - Device 1 Unit 1_0:Invalid Fabric Width for GTHE1_QUAD_X0Y0_0- XSDB interface may be corrupted" |
| (Xilinx Answer 40486) | 13.1 ChipScope Pro IBERT - Generation fails at NGDBuild with "ERROR:NgdBuild:604" and "ERROR:NgdBuild:456" |
| (Xilinx Answer 39512) | 12.x/13.x ChipScope IBERT GTH - "ERROR:sim - runPar : IBERT:par: Timing for this design was not met..." |
| (Xilinx Answer 41734) | 12.x/13.1 ChipScope IBERT - Virtex-6 GTH Transceivers Production Silicon Support |
| (Xilinx Answer 42131) | Virtex-6 FPGA GTH Transceivers - Incorrect Attribute Settings Could Affect Performance |
| (Xilinx Answer 45381) | 45381 - ChipScope GTX IBERT, Virtex-5 FXT/TXT- Performing a sweep test on DFETAP values doesn't work correctly |
| (Xilinx Answer 45646) | 13.1, 13.2, 13.3 - Kintex-7/Virtex-7 - GTX IBERT will not work when using 32-bit DATA_WIDTH |
| (Xilinx Answer 45648) | 13.1, 13.2, 13.3, 13.4 - Virtex-7/Kintex-7 - Using KC705 or VC705 "Board Configuration Setting" in GTX IBERT uses incorrect I/O Standard for system clock |
| (Xilinx Answer 45674) | 13.4 and earlier - Virtex-7 and Kintex-7 - GTX IBERT core with 562.5 MHz refclk may cause map error |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 47005 | Xilinx ChipScope Solution Center - Top Issues | N/A | N/A |
| 41734 | 12.x/13.1 ChipScope IBERT - Virtex-6 GTH Transceivers Production Silicon Support | N/A | N/A |