AR# 42444

描述

This Design Advisory was most recently updated on January 25th, 2012,with the details in the [Update - Added Timing Check] section below. All other information remains unchanged (see revision history below).

The ISE 11.x, 12.x, and 13.1 TRCE/Timing Analyzer tools do not correctly analyze certain control signals and address lines ofthe Virtex-6 36 kb block RAM (RAMB36E1),18 kb block RAM(RAMB18E1), 36 kb FIFO (FIFO36E1), and 18 kb FIFO (FIFO18E1) when used in SDP, TDP, or ECC modes, potentially resulting in unreported setup and hold time violations.

The unreported violations can result in read and write errors and are not reported in the unconstrained path report section of the timing report.

All aspect ratio configurations of the 36 kb block RAM (RAMB36E1), the 18 kb block RAM(RAMB18E1), 36 kb FIFO (FIFO36E1),and the 18 kb FIFO (FIFO18E1) are affected by this issue.

Previous architectures or 7 Series FPGAs are not impacted by this issue.

[Update - Added Timing Check] In addition to the details above, a setup/hold timing check on the reset pin of the optional block RAM output registers in the RAMB18E1 instance has been added in the ISE 13.4 software release (RAMB36E1 already has this check).

In the majority of cases, the block RAM output register is not utilized, so this timing check is not required. When this block RAM output register is explicitly added (by using the DO[A|B]_REG attribute), this reset path is usually covered by a multi-cycle timing (FROM:TO) constraint.

However, there is a small possibility that existing designs that are simply re-timed with ISE Design Suite13.4 will report a setup/hold violation. 

It is recommended to check the Timing Analysis of potentially affected designs in the ISE 13.4 software, although the impact is expected to be very minimal.

All Virtex-6 FPGA designs must be reviewed to assess whether this issue affects the design.

解决方案

Following is an overview of the steps to take to detect the issue described above which is fixed in ISE 13.2 design tools:

• Check for block RAM and FIFO utilization
• Assess timing analysis results with patched software tools or ISE 13.2 design tools
• Update failing designs

Details

To identify whether a design is affected by the issue:

1. Check the MAP report (.MRP) generated by the ISE implementation tools.
   • If the sections under 'Specific Feature Utilization' listed as 'Number of RAMB36E1/FIFO36E1s' and 'Number of RAMB18E1/FIFO18E1s' show '0', the design does not contain block RAMs or FIFOs and is not affected by this issue.
   • If the 'Number of RAMB36E1/FIFO36E1s' or 'Number of RAMB18E1/FIFO18E1s' shows '1' or more, continue following the steps below.
2. If using ISE 13.1 or previous software versions, download and install the appropriate patch:
   
   • Patch for 13.1: ar42444_cr612073_timing_spd_o40e_13_1_all.zip
   • Patch for 12.4: ar42444_cr612073_timing_spd_m81d_12_4_all.zip
   • Patch for 12.3: ar42444_cr612073_timing_spd_m70d_12_3_all.zip
   • Patch for 12.2: ar42444_cr612073_timing_spd_m63c_12_2_all.zip
3. Run the design again through timing analysis using ISE 13.2 design tools or the patched software tools.
   • Example command line: trce-e5 design1.ncd timing.pcf or timingan
4. Analyze timing analysis results.
   • If the design passes timing analysis with no errors, no further action is necessary. Designs in the field are not affected by this issue if timing analysis is passed. Designs in progress should continue using the patched software tools or ISE 13.2 design tools for further development.
   • If the design fails timing after running timing analysis with the patch or ISE 13.2 design tools, the design must be updated so that it passes timing analysis, and a new bitstream must be generated.
   • Note that if you disabled reg_sr_r, these paths will not be disabled with this patch.

There are various methods of updating a failing design using the patched software or ISE 13.2 design tools.

ISE and PlanAhead Software Users

• Option 1 (ISE tools only, this option fixes all errors for most affected designs)
  • Re-run the Place-and-Route process.
  • If timing analysis passes with the newly routed design, continue to bitstream creation.
• Option 2 (this option fixes all errors for most affected designs)
  • Re-run the MAP and Place-and-Route processes.
  • If timing analysis passes with the newly placed and routed design, continue to bitstream creation.
• Option 3
  • Use traditional timing closure techniques such as SmartXplorer to close timing.
• Option 4 (for advanced users looking to minimize changes in existing designs)
  • Use FPGA Editor to re-route failing paths.

Command Line Users

• Option 1
  • Route the design in PAR with Re-Entrant Routing.
    • Example command line: par-k original.ncd new_output.ncd original.pcf
  • If timing analysis passes with the newly routed design, continue to bitstream creation.
• Option 2 (This option fixes all errors for most affected designs)
  • Route the design in PAR.
  • If timing analysis passes with the newly routed design, continue to bitstream creation.
• Option 3 (This option fixes all errors for most affected designs)
  • Run the design through MAP and PAR.
    • Example command lines:
      • Map: map original.ngd
      • Par: par input.ncd output.ncd input.pcf
  • If timing analysis passes with the newly routed design, continue to bitstream creation.
• Option 4
  • Use traditional timing closure techniques such as SmartXplorer to close timing.
• Option 5 (for advanced users looking to minimize changes in existing designs)
  • Use FPGA Editor to re-route failing paths.

For assistance with identifying or updating affected designs, contact Xilinx Technical Support.

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